- 30 Sep, 2020 7 commits
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Ramesh Errabolu authored
waves that are in flight. [Why] Allow user to know how many compute units (CU) are in use at any given moment. [How] Read registers of SQ that give number of waves that are in flight of various queues. Use this information to determine number of CU's in use. Signed-off-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-By:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jiansong Chen authored
gfxoff is temporarily disabled for navy_flounder, since at present the feature caused some tdr when performing display operations. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Guchun Chen authored
The same ECC check has been executed in amdgpu_ras_init for vega10, prior to gmc_v9_0_late_init. v2: drop all atombios helper callings v3: use bit operation v4: correct inline comment, remove parity check statement v5: squash in build fix Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
Add code to gracefuly handle any pipe reassignment occuring on dcn3 hardware. This should only happen when new surfaces are used for an update rather than old ones updated. Fixes: 69fc1f4b ("amd/drm/display: avoid dcn3 on flip opp change for slave pipes") Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Oak Zeng authored
gfxhub functions are now called from function pointers, instead of from asic-specific functions. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
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Ramesh Errabolu authored
[Why] Allow user to know number of compute units (CU) that are in use at any given moment. [How] Read registers of SQ that give number of waves that are in flight of various queues. Use this information to determine number of CU's in use. Signed-off-by:
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Ramesh Errabolu authored
[Why] Header file exports functions get_gpu_clock_counter(), get_cu_info() and select_se_sh() that are defined to be static Signed-off-by:
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- 29 Sep, 2020 19 commits
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Kent Russell authored
The VG20 DIDs 66a0, 66a1 and 66a4 are used for various SKUs that may or may not have the FRU EEPROM on it. Parse the VBIOS to check for server SKU variants (D131 or D134) until a more general solution can be determined. v2: Remove string-based logic, correct the VBIOS string comment Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Alex Deucher authored
The state array is in the reverse order compared to other asics (high to low rather than low to high). Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1313Reviewed-by:
Prike Liang <Prike.Liang@amd.com> Signed-off-by:
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Dirk Gouders authored
Commit 78fe9f63 ("drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU Versions") added a call to rn_vbios_smu_get_smu_version() to set clk_mgr->smu_ver. That field is initialized prior to the if-statement, already. Fixes: 78fe9f63 (drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU Versions) Signed-off-by:
Dirk Gouders <dirk@gouders.net> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Sung Lee <sung.lee@amd.com> Cc: Yongqiang Sun <yongqiang.sun@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Xiaojian Du authored
drm/amd/powerplay: add one sysfs file to support the feature to modify gfx clock on Raven/Raven2/Picasso APU. This patch is to add one sysfs file -- "pp_od_clk_voltage" for Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10. This sysfs file supports the feature to modify gfx engine clock(Mhz units), it can be used to configure the min value and the max value for gfx clock limited in the safe range. Command guide: echo "s level clock" > pp_od_clk_voltage s - adjust teh sclk level level - 0 or 1, "0" represents the min value, "1" represents the max value clock - the clock value(Mhz units), like 400, 800 or 1200, the value must be within the OD_RANGE limits. Example: $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz $ echo "s 0 600" > pp_od_clk_voltage $ echo "s 1 1000" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 600Mhz 1: 1000Mhz OD_RANGE: SCLK: 200MHz 1400MHz Signed-off-by:Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Shashank Sharma authored
This patch adds a new trace event to track the PTE update events. This specific event will provide information like: - start and end of virtual memory mapping - HW engine flags for the map - physical address for mapping This will be particularly useful for memory profiling tools (like RMV) which are monitoring the page table update events. V2: Added physical address lookup logic in trace point V3: switch to use __dynamic_array added nptes int the TPprint arguments list added page size in the arg list V4: Addressed Christian's review comments add start/end instead of seg use incr instead of page_sz to be accurate V5: Addressed Christian's review comments: add pid and vm context information in the event V6: Re-sequence the variables (put pid and ctx_id first) Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:Christian König <christian.koenig@amd.com> Signed-off-by:
Shashank Sharma <shashank.sharma@amd.com> Reviewed-by:
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Guchun Chen authored
It should be one copy-paste typo. Signed-off-by:
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Jean Delvare authored
A recent attempt to fix a ref count leak in amdgpu_display_crtc_set_config() turned out to be doing too much and "fixed" an intended decrease as if it were a leak. Undo that part to restore the proper balance. This is the very nature of this function to increase or decrease the power reference count depending on the situation. Consequences of this bug is that the power reference would eventually get down to 0 while the display was still in use, resulting in that display switching off unexpectedly. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Fixes: e008fa6f ("drm/amdgpu: fix ref count leak in amdgpu_display_crtc_set_config") Cc: stable@vger.kernel.org Cc: Navid Emamdoost <navid.emamdoost@gmail.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Jason Yan authored
This addresses the following sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2740:6: warning: symbol 'dce110_set_cursor_position' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2785:6: warning: symbol 'dce110_set_cursor_attribute' was not declared. Should it be static? Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Jason Yan <yanaijie@huawei.com> Signed-off-by:
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Jason Yan authored
This addresses the following sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_hw_sequencer.c:180:26: warning: symbol 'get_color_space_type' was not declared. Should it be static? Reviewed-by:
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Dmytro Laktyushkin authored
At the moment on flip opp reassignment does not work in all cases for non root pipes. This change simply makes sure we prefer pipes not used previously when splitting in dcn3. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Eric Bernstein <eric.bernstein@amd.com> Signed-off-by:
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Chiawen Huang authored
[Why] Vbios uses preferred timing to turn on edp but OS could use other timing. If change pixel clock when link active, there is unexpected garbage on monitor. [How] Once pixel clock changed, the driver needs to disable stream. Signed-off-by:
Chiawen Huang <chiawen.huang@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Anthony Koo authored
[Header Changes] - Definition for retaining ABM settings during disable - Addition of some new AUX interface definitions - Addition of some outbox definitions Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] At the moment, some tests are failing because cur_link_settings is invalid. As a workaround, add an option to force dio disable. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Joshua Aberback authored
[Why] Currently, when full p-state changes are not supported, DLG parameters are calculated for no p-state support at all. However, we are required to always support dummy p-state changes, so we should instead calculate DLG based on dummy p-state latency when full p-state is unsupported. This behaviour already exists for DCN2. [How] - move DLG calculation inside WM calculation - if p-state unsupported, do not recalculate for set A, instead copy from set C, and perform DLG calculation with dummy p-state latency Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Chiawen Huang authored
[Why] Vbios uses preferred timing to turn on edp but OS could use other timing. If change pixel clock when link active, there is unexpected garbage on monitor. [How] Once pixel clock changed, the driver needs to disable stream. Signed-off-by:
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Wyatt Wood authored
[Why] Some debug bits are not being copied from driver to fw. [How] Copy debug bits properly. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Eric Bernstein authored
Signed-off-by:
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Alvin Lee authored
[Why] HW team measurement requires updating values [How] Update bounding box values Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
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- 25 Sep, 2020 14 commits
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Evan Quan authored
Revert the guilty change introduced by the commit below: drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2) Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Alex Deucher authored
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return value of ‘sysfs_create_group’, declared with attribute warn_unused_result [-Wunused-result] 1284 | sysfs_create_group(&adev->dev->kobj, &group); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ v2: just print an error for sysfs group creation failure Acked-by:Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Guchun Chen authored
Merge ras sysfs creation together by calling sysfs_create_group once, as sysfs_update_group may not work properly as expected. v2: improve commit message Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Signed-off-by:
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Tiecheng Zhou authored
In FLR routine, init_data_exchange is called at reset_sriov while fini_data_exchange is not. This will duplicating work thread. So call fini_data_exchange before reset for SRIOV Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by:
Bokun Zhang <Bokun.Zhang@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Bokun Zhang authored
- Refactor the driver code to use amdgpu_virt_read_pf2vf_data and amdgpu_virt_write_vf2pf_data instead of writing all code in one function (which is the old amdgpu_virt_init_data_exchange) - Adding a new transaction method for VF2PF message between host and guest driver. Guest side will periodically update VF2PF message in the framebuffer. In the new header, we include guest ucode information, guest framebuffer usage, and engine usage - Clean up the old macros since they will cause compile error if the new transaction method is used v2: squash in build fix Signed-off-by:
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Bokun Zhang authored
- Update guest side VF2PF interface header file Signed-off-by:
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Ryan Taylor authored
Documents PP_FEATURE_MASK enum. Provides instructions on how to use ppfeaturemasks. v2: improve enum definitions and add kernel command line parameters to ppfeaturemask instructions v3: fix alignment issues Signed-off-by:Ryan Taylor <ryan.taylor@amd.com> Reviewed-by:
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John Clements authored
disable UMC RAS in lieu of stability issues on certain sku Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Alex Deucher authored
This allows us to set different defaults on a per asic basis. This way we can enable noretry on dGPUs where it can increase performance in certain cases and disable it on chips where it can be problematic. For now the default is 0 for all asics, but we may want to try and enable it again for newer dGPUs. Reviewed-by:
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Alex Deucher authored
This will allow us to have different defaults per asic in a future patch. Reviewed-by:
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Alex Deucher authored
Properly handle clang and older versions of gcc. Fixes: e77165bf ("drm/amd/display: Add DCN3 blocks to Makefile") Acked-by:
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Emily.Deng authored
Signed-off-by:
Emily.Deng <Emily.Deng@amd.com> Reviewed-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
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Jingwen Chen authored
smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate sw_init for navi12. v2: skip above fw in SRIOV for vega10 and sienna_cichlid v3: directly skip psp fw loading in SRIOV Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by:
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Jingwen Chen authored
smc fw is not needed in SRIOV, thus driver should not try to get smc fw data. Signed-off-by:
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