- 28 Sep, 2022 5 commits
-
-
Paul Bolle authored
A check for CONFIG_DEBUG_LL_SER3 was added in v2.5.43. But the related symbol DEBUG_LL_SER3 was already removed in v2.5.8. This check has always evaluated to false. Remove it. Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
-
Dmitry Baryshkov authored
To ease debugging of PSCI supported features, add debugfs file called 'psci' describing PSCI and SMC CC versions, enabled features and options. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Mark Brown <broonie@kernel.org> Reviewed-by:
Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20220926110758.666922-1-dmitry.baryshkov@linaro.org' Signed-off-by:
-
Dmitry Baryshkov authored
The function psci_pd_try_set_osi_mode() will print an error if enabling OSI mode fails. To ease debugging PSCI issues print corresponding message if switching to PC mode fails too. Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com> Reviewed-by:
Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220926110249.666813-1-dmitry.baryshkov@linaro.org' Signed-off-by:
-
Arnd Bergmann authored
Merge tag 'memory-controller-drv-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v6.1, part 2 Improvements in Synopsys DesignWare Universal Multi-Protocol Memory Controller Devicetree bindings. The bindings are being split into one related to Synopsys core and into quite different derivative Zynq A05 DDR Memory Controller. Extend the Synopsys bindings with additional properties to match upcoming new device support (Baikal-T1 support). * tag 'memory-controller-drv-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: dt-bindings: memory: snps,dw-umctl2-ddrc: Extend schema with IRQs/resets/clocks props dt-bindings: memory: snps,dw-umctl2-ddrc: Replace opencoded numbers with macros dt-bindings: memory: snps,dw-umctl2-ddrc: Use more descriptive device name dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support Link: https://lore.kernel.org/r/20220926105023.119781-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
-
Arnd Bergmann authored
Merge tag 'v6.1-rockchip-drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/drivers Some binding additions for rk3128 and rv1126 * tag 'v6.1-rockchip-drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: soc: rockchip: grf: add rockchip,rk3128-grf dt-bindings: arm: rockchip: pmu: add rockchip,rk3128-pmu dt-bindings: soc: rockchip: Document RV1126 pmugrf dt-bindings: soc: rockchip: Document RV1126 grf Link: https://lore.kernel.org/r/3790767.LM0AJKV5NW@philSigned-off-by:
-
- 23 Sep, 2022 8 commits
-
-
Arnd Bergmann authored
Merge tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc/tegra: cbb: Changes for v6.1-rc1 This introduces the CBB driver that is used to provide (a lot of) information about SErrors when things go wrong, instead of the kernel just crashing or hanging. * tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: cbb: Add support for Tegra241 (Grace) soc/tegra: cbb: Add driver for Tegra234 CBB 2.0 soc/tegra: cbb: Add CBB 1.0 driver for Tegra194 soc/tegra: Set ERD bit to mask inband errors Link: https://lore.kernel.org/r/20220916101957.1635854-2-thierry.reding@gmail.comSigned-off-by:
-
https://github.com/hisilicon/linux-hisiArnd Bergmann authored
HiSilicon driver updates for 6.1: - some small improvements to the hisi_lpc driver * tag 'hisi-drivers-for-6.1' of https://github.com/hisilicon/linux-hisi: bus: hisi_lpc: Use platform_device_register_full() bus: hisi_lpc: Don't guard ACPI IDs with ACPI_PTR() bus: hisi_lpc: Correct error code for timeout bus: hisi_lpc: Use devm_platform_ioremap_resource bus: hisi_lpc: Don't dereference fwnode handle Link: https://lore.kernel.org/r/631FE463.6070701@hisilicon.comSigned-off-by:
-
Arnd Bergmann authored
Merge tag 'qcom-drivers-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver updates for 6.1 The icc-bwmon driver is expected to support measuring LLCC/DDR bandwidth on SDM845 and SC7280. The LLCC driver is extended to provide per-platform register mappings to the LLCC EDAC driver. The QMI encoder/decoder is updated to allow the passed qmi_elem_info to be const. Support for SDM845 is added to the sleep stats driver. Power-domains for the SM6375 platform is added to RPMPD and the platform is added to socinfo, together with the PM6125 pmic id. A couple of of_node reference issues are corrected in the smem state and smsm drivers. The Qualcomm SCM driver binding is converted to YAML. * tag 'qcom-drivers-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (29 commits) soc: qcom: rpmpd: Add SM6375 support dt-bindings: power: rpmpd: Add SM6375 power domains firmware: qcom: scm: remove unused __qcom_scm_init declaration dt-bindings: power: qcom,rpmpd: drop non-working codeaurora.org emails soc: qcom: icc-bwmon: force clear counter/irq registers soc: qcom: icc-bwmon: add support for sc7280 LLCC BWMON dt-bindings: interconnect: qcom,msm8998-bwmon: Add support for sc7280 BWMONs soc: qcom: llcc: Pass LLCC version based register offsets to EDAC driver soc: qcom: llcc: Rename reg_offset structs to reflect LLCC version soc: qcom: qmi: use const for struct qmi_elem_info soc: qcom: icc-bwmon: remove redundant ret variable dt-bindings: soc: qcom: stats: Document SDM845 compatible soc: qcom: stats: Add SDM845 stats config and compatible dt-bindings: firmware: document Qualcomm SM6115 SCM soc: qcom: Make QCOM_RPMPD depend on OF dt-bindings: firmware: convert Qualcomm SCM binding to the yaml soc: qcom: socinfo: Add PM6125 ID soc: qcom: socinfo: Add an ID for SM6375 soc: qcom: smem_state: Add refcounting for the 'state->of_node' soc: qcom: smsm: Fix refcount leak bugs in qcom_smsm_probe() ... Link: https://lore.kernel.org/r/20220921155753.1316308-1-andersson@kernel.orgSigned-off-by:
-
Arnd Bergmann authored
Merge tag 'v6.0-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers pmic-wrapper: - add support for mt8188 SVS: - several driver cleanups power-domain: - several cleanups of the dt-bindings and driver mutex: - add support to mt6795 disp mutex - add support for mt8186 mdp3 mutex * tag 'v6.0-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: soc: mediatek: Add mmsys func to adapt to dpi output for MT8186 soc: mediatek: mutex: Add support for MT6795 Helio X10 display mutex dt-bindings: soc: mediatek: Add display mutex support for MT6795 soc: mediatek: mutex: Add mt8186 mutex mod settings for mdp3 dt-bindings: soc: mediatek: Add mdp3 mutex support for mt8186 soc: mediatek: pm-domains: Simplify some error message soc: mediatek: mtk-svs: Explicitly include bitfield header soc: mediatek: mtk-svs: Use bitfield access macros where possible soc: mediatek: mtk-svs: Commonize t-calibration-data fuse array read dt-bindings: power: mediatek: Update maintainer list dt-bindings: power: mediatek: Support naming power controller node with unit address dt-bindings: power: mediatek: Refine multiple level power domain nodes soc: mediatek: mtk-svs: Use devm variant for dev_pm_opp_of_add_table() soc: mediatek: mtk-svs: Drop of_match_ptr() for of_match_table soc: mediatek: mtk-svs: Remove hardcoded irqflags soc: mediatek: mtk-svs: Switch to platform_get_irq() dt-bindings: soc: mediatek: pwrap: add compatible for mt8188 soc: mediatek: Let PMIC Wrapper and SCPSYS depend on OF Link: https://lore.kernel.org/r/498fe3e5-a237-121a-d500-fbb0994906cb@gmail.comSigned-off-by:
-
Arnd Bergmann authored
Merge tag 'sunxi-drivers-for-6.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/drivers sunxi SRAM driver changes: - minor code refactor - support for Allwinner D1 * tag 'sunxi-drivers-for-6.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: soc: sunxi: sram: Add support for the D1 system control soc: sunxi: sram: Export the LDO control register soc: sunxi: sram: Save a pointer to the OF match data soc: sunxi: sram: Return void from the release function soc: sunxi: sram: Fix debugfs info for A64 SRAM C soc: sunxi: sram: Fix probe function ordering issues soc: sunxi: sram: Prevent the driver from being unbound soc: sunxi: sram: Actually claim SRAM regions Link: https://lore.kernel.org/r/YyeOthH4y8wy8A8R@kista.localdomainSigned-off-by:
-
Arnd Bergmann authored
Merge tag 'imx-drivers-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers change for 6.1: - Update i.MX8MP blk-ctrl driver to handle PCIe PHY reset bit. - Add interconnect support into i.MX8MP blk-ctrl driver, so that i.MX8MP NoC can be set up properly after related power domain is up. - Add blk-ctrl support for i.MX8MP HDMI HDCP/HRV and VPU block. - Add i.MX93 SRC power domain and MEDIA blk-ctrl driver. - Update imx8m-blk-ctrl driver to use genpd_xlate_onecell. * tag 'imx-drivers-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (26 commits) soc: imx: add i.MX93 media blk ctrl driver soc: imx: add i.MX93 SRC power domain driver soc: imx: imx8m-blk-ctrl: Use genpd_xlate_onecell soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets soc: imx: imx8m-blk-ctrl: add i.MX8MP VPU blk ctrl soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV_MWR soc: imx: add icc paths for i.MX8MP hsio/hdmi blk ctrl soc: imx: add icc paths for i.MX8MP media blk ctrl dt-bindings: arm: imx: update fsl.yaml for imx8dxl dt-bindings: firmware: add missing resource IDs for imx8dxl dt-bindings: arm: Add i.MX8M Mini Gateworks GW7904 board dt-bindings: soc: add i.MX93 mediamix blk ctrl dt-bindings: soc: add i.MX93 SRC dt-bindings: mfd: syscon: Add i.MX93 blk ctrl system registers dt-bindings: arm: fsl: Add MSC SM2S-IMX8PLUS SoM and SM2-MB-EP1 Carrier dt-bindings: arm: fsl: Add Kontron BL i.MX8MM OSM-S board dt-bindings: arm: fsl: Rename compatibles for Kontron i.MX8MM SoM/board dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl dt-bindings: soc: imx: add interconnect property for i.MX8MM vpu blk ctrl dt-bindings: soc: imx: drop minItems for i.MX8MM vpu blk ctrl ... Link: https://lore.kernel.org/r/20220918092806.2152700-2-shawnguo@kernel.orgSigned-off-by:
-
Arnd Bergmann authored
Merge tag 'tegra-for-6.1-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers firmware: tegra: Changes for v6.1-rc1 A simple cleanup for user memory usage in the BPMP debugfs support. * tag 'tegra-for-6.1-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: firmware: tegra: Switch over to memdup_user() Link: https://lore.kernel.org/r/20220916101957.1635854-3-thierry.reding@gmail.comSigned-off-by:
-
Arnd Bergmann authored
Merge tag 'tegra-for-6.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc/tegra: Changes for v6.1-rc1 This contains an assortment of small fixes and cleanups. One new feature is introduced in the form of simple wake events which are needed to wake the system from sleep on USB port events. * tag 'tegra-for-6.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Check device node status property soc/tegra: pmc: Use devm_clk_get_optional() soc/tegra: fuse: Drop Kconfig dependency on TEGRA20_APB_DMA soc/tegra: pmc: Add USB port wake events for Tegra194 soc/tegra: pmc: Add support for simple wake events soc/tegra: pmc: Remove leading space soc/tegra: fuse: Add missing of_node_put() soc/tegra: fuse: Add missing of_node_put() in tegra_init_fuse() Link: https://lore.kernel.org/r/20220916101957.1635854-1-thierry.reding@gmail.comSigned-off-by:
-
- 21 Sep, 2022 4 commits
-
-
Serge Semin authored
First of all the DW uMCTL2 DDRC IP-core supports the individual IRQ lines for each standard event: ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection, Scrubber-Done signal, DFI Parity/CRC Error. It's possible that the platform engineers merge them up in the IRQ controller level. So let's add both configuration support to the DT-schema. Secondly the DW uMCTL2 DDRC IP-core can have clock sources like APB reference clock, AXI-ports clock, main DDRC core reference clock and Scrubber low-power clock. In addition to that each clock domain can have a dedicated reset signal. Let's add the properties for at least the denoted clock sources and the corresponding reset controls. Note the IRQs and the phandles order is deliberately not fixed since some of the sources may be absent depending on the IP-core synthesize parameters and the particular platform setups. Signed-off-by:
Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220910195659.11843-3-Sergey.Semin@baikalelectronics.ru
-
Serge Semin authored
Xilinx ZynqMP DDRC-based example contains the opencoded numerical literals in the IRQ lines definition. It doesn't seem justified since the corresponding platform has well defined ARM GIC interface. Let's replace the numbers with the corresponding macros then. Signed-off-by:
-
Serge Semin authored
The DT-schema name and the corresponding generic compatible string look inappropriate in the current DW uMCTL2 DDRC DT-bindings: 1. DT-schema name contains undefined vendor-prefix. It's supposed to be "snps", not "synopsys". 2. DT-schema name has "ecc" suffix. That is a device property, and has nothing to do with the controller actual name. 3. The controller name is different. It's DW uMCTL2 DDRC. Just DDRC doesn't identify the IP-core in subject. 4. There is no much point in using the IP-core version in the device name since it can be retrieved from the corresponding device CSR. Moreover the DW uMCTL2 DDRC driver doesn't differentiate the IP-core version at the current state. In order to fix all the inconsistencies described above we suggest to rename the DT-schema to "snps,dw-umctl2-ddrc.yaml", deprecate the compatible string "snps,ddrc-3.80a" and define a new generic device name as "snps,dw-umctl2-ddrc". Signed-off-by:
-
Serge Semin authored
The Zynq A05 DDRC controller has nothing in common with DW uMCTL2 DDRC: the CSRs layout is absolutely different and it doesn't support IRQs unlike DW uMCTL2 DDR controller of all versions (v1.x, v2.x and v3.x). Thus there is no any reason to have these controllers described in the same bindings. Let's split the DT-schema up. Note since the synopsys,ddrc-ecc.yaml schema describes the Synopsys DW uMCTL2 DDR controller only, we need to accordingly fix the device descriptions. Signed-off-by:
-
- 18 Sep, 2022 4 commits
-
-
Samuel Holland authored
D1 has a single EMAC and some LDOs that need to be exported. Acked-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by:
Samuel Holland <samuel@sholland.org> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
-
Samuel Holland authored
Some newer Allwinner SoCs contain internal LDOs managed by a register in the system control MMIO space. Export this from the regmap in addtion to the EMAC register. Use generic names now that the regmap is no longer EMAC-specific. Acked-by:
-
Samuel Holland authored
It is inefficient to match the compatible string every time the regmap is accessed. Acked-by:
-
Samuel Holland authored
There is no point in returning an error here, as the caller can do nothing about it. In fact, all callers already ignore the return value. Acked-by:
-
- 17 Sep, 2022 19 commits
-
-
Hector Martin authored
This allows a client to receive messages in atomic context, by polling. Signed-off-by:
Hector Martin <marcan@marcan.st> Signed-off-by:
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by:
Sven Peter <sven@svenpeter.dev> Reviewed-by:
Eric Curtin <ecurtin@redhat.com> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
-
Peng Fan authored
Add i.MX93 mediamix blk ctrl support. i.MX93 mediamix blk ctrl has registers to set QoS(priority) value. It support default QoS value and cfg QoS value. Set an initial value from i.MX design team. If LCDIF/ISI/PXP wanna a different QoS value in future, they could use interconnect to request bandwidth. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
-
Peng Fan authored
Support controlling power domain managed by System Reset Controller(SRC). Current supported power domain is mediamix power domain. Signed-off-by:
-
Peng Fan authored
Simplify driver by using genpd_xlate_onecell instead of driver specific xlate function. Signed-off-by:
-
Lucas Stach authored
Dessert the PHY reset when powering up the domain and put it back into reset when the domain is powered down. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by:
-
Peng Fan authored
i.MX8MP has a VPU blk ctrl module that could supply clk and reset to VPU, so add support for it. Signed-off-by:
-
Peng Fan authored
i.MX8MP HDMI supports HDCP and HRV_MWR(HDMI RX Video Memory Write Master for RXRX validation), so add them. Signed-off-by:
-
Peng Fan authored
Add interconnect paths for i.MX8MP hsio/hdmi blk ctrl Signed-off-by:
-
Peng Fan authored
Add interconnect paths for i.MX8MP media blk ctrl Signed-off-by:
-
Shenwei Wang authored
i.MX8DXL is a device targeting the automotive and industrial market segments. The chip is designed to achieve both high performance and low power consumption. It has a dual (2x) Cortex-A35 processor. Signed-off-by:
Shenwei Wang <shenwei.wang@nxp.com> Acked-by:
-
Shenwei Wang authored
Add the missing resource IDs for imx8dxl. Signed-off-by:
-
Tim Harvey authored
Add DT compatible string for i.MX8M Mini based Gateworks GW7904 board. Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Acked-by:
-
Peng Fan authored
Add DT bindings for i.MX93 MEDIAMIX BLK CTRL. Reviewed-by:
-
Peng Fan authored
Add bindings for i.MX93 System Reset Controller(SRC). SRC supports resets and power gating for mixes. Reviewed-by:
-
Peng Fan authored
Document i.MX93 BLK CTRL system registers. Signed-off-by:
-
Martyn Welch authored
Add DT compatible strings for a combination of the 14N0600E variant of the Avnet (MSC branded) SM2S-IMX8PLUS SoM on it's own and in combination with the SM2-MB-EP1 carrier board. Signed-off-by:
Martyn Welch <martyn.welch@collabora.com> Acked-by:
-
Frieder Schrempf authored
Add bindings for the Kontron BL i.MX8MM OSM-S board. Signed-off-by:
Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by:
-
Frieder Schrempf authored
This updates the bindings in order to use names for the boards that follow the latest convention used by Kontron marketing. By updating we make sure, that we can maintain this more easily in future and make sure that the proper devicetree can be selected for the hardware. Signed-off-by:
-
Peng Fan authored
i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse the i.MX8MM VPU blk ctrl yaml file. And add description for the items. Reviewed-by:
-
