- 26 Feb, 2024 1 commit
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.9 (take two) - Add support for the R-Car V4M (R8A779H0) SoC, - Add support for suspend/resume on the RZ/G2L family, - Miscellaneous fixes and improvements. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 21 Feb, 2024 7 commits
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Krzysztof Kozlowski authored
Use proper model name in SM8650 LPASS pin controller Kconfig entry. Cc: <stable@vger.kernel.org> Fixes: c4e47673 ("pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS") Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240216102435.89867-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Geert Uytterhoeven authored
The conversion to DEFINE_NOIRQ_DEV_PM_OPS() lost the ability of the compiler to optimize away the struct dev_pm_ops object when it is not needed. Fix this by replacing the use of pm_sleep_ptr() by a custom wrapper. Fixes: 727eb02e ("pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/6238a78e32fa21f0c795406b6cba7bce7af92577.1708513940.git.geert+renesas@glider.be
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Claudiu Beznea authored
pinctrl-rzg2l driver is used on RZ/G3S which support deep sleep states where power to most of the SoC components is turned off. For this add suspend/resume support. This involves saving and restoring configured registers along with disabling clock in case there is no pin configured as wakeup sources. To save/restore registers 2 caches were allocated: one for GPIO pins and one for dedicated pins. On suspend path the pin controller registers are saved and if none of the pins are configured as wakeup sources the pinctrl clock is disabled. Otherwise it remains on. On resume path the configuration is done as follows: 1/ setup PFCs by writing to registers on pin based accesses 2/ setup GPIOs by writing to registers on port based accesses and following configuration steps specified in hardware manual 3/ setup dedicated pins by writing to registers on port based accesses 4/ setup interrupts. Because interrupt signals are routed to IA55 interrupt controller and IA55 interrupt controller resumes before pin controller, patch restores also the configured interrupts just after pin settings are restored to avoid invalid interrupts while resuming. Signed-off-by:
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by:
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Claudiu Beznea authored
The pinctrl-rzg2l driver accesses gpio_chip.irq, which is available only if CONFIG_GPIOLIB_IRQCHIP=y, and uses APIs that are defined only if CONFIG_IRQ_DOMAIN_HIERARCHY=y (irq_chip_*_parent() APIs). On ARCH_RZG2L, CONFIG_IRQ_DOMAIN_HIERARCHY is selected anyway, e.g. by CONFIG_ARM_GIC_V3, but CONFIG_GPIOLIB_IRQCHIP is not (it is on R-Car). Make this explicit at the driver level for a clearer view of the dependencies. Signed-off-by:
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Biju Das authored
Currently on irq_disable(), we are disabling gpio interrupt enable(ISEL). That means the pin is just gpio input and not gpio input interrupt any more. So, move configuring ISEL in rzg2l_gpio_child_to_parent_hwirq()/ rzg2l_gpio_irq_domain_free() so that the pin will be gpioint always even during irq_disable(). Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
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Biju Das authored
Simplify rzg2l_gpio_irq_{en,dis}able() by adding a helper function rzg2l_gpio_irq_endisable(). Signed-off-by: -
Biju Das authored
Configure GPIO interrupt as input mode. Also if the bootloader sets gpio interrupt pin as function, override it as gpio. Signed-off-by:
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- 20 Feb, 2024 14 commits
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Cong Dang authored
Add pins, groups and functions for Audio on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
Cong Dang <cong.dang.xn@renesas.com> Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for the PCIe Controller on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for the CAN-FD interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for the PWM and 16-Bit Timer Pulse Units (TPU) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for the I2C Bus Interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for the High Speed Serial Communication Interfaces with FIFO (HSCIF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for the baud rate generation clock pins (SCIF_CLK) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for the Serial Communication Interfaces with FIFO (SCIF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for the QSPI functionality proviced by the SPI Multi I/O Bus Controller (RPC-IF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for the SD Card/MMC Interface on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add pins, groups and functions for Ethernet AVB on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Cong Dang authored
Add initial pin control support for the R-Car V4M (R8A779H0) SoC, including bias, drive strength and voltage control. Signed-off-by:
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Geert Uytterhoeven authored
Document support for the Pin Function Controller (PFC) in the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/56685dc04af3cee7cb3751e855ed5b3679b14122.1706264667.git.geert+renesas@glider.be
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- 13 Feb, 2024 1 commit
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.9 - Add pin groups for SCIF_CLK2 on R-Car V4H, - Add support for port pins P19 to P28 on RZ/Five, - Miscellaneous fixes and improvements. Signed-off-by:
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- 09 Feb, 2024 3 commits
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Arturas Moskvinas authored
GPINTEN register contains information about GPIOs with enabled interrupts no need to check other GPIOs for changes. Signed-off-by:
Arturas Moskvinas <arturas.moskvinas@gmail.com> Link: https://lore.kernel.org/r/20240201141406.32484-2-arturas.moskvinas@gmail.comSigned-off-by:
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Naresh Solanki authored
Update maxItems to 60 for gpio-reserved-ranges to allow multiple gpio reserved ranges. Add input-enable property to allow configuring a pin as input. Also update example. Signed-off-by:
Naresh Solanki <naresh.solanki@9elements.com> Reviewed-by:
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Rob Herring authored
The structure of the NVIDIA Tegra234 common pinmux schema doesn't work for restricting properties because a child node schema can't be extended with additional properties from another schema defining the same child node. The 2 child node schemas are evaluated independently as the schemas are not recursively combined in any way. As the common schema is almost all the child node schema anyways, just remove the parent node from the common schema. Then add 'reg' and adjust the $ref's in the users of the common schema. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240202223454.1667383-1-robh@kernel.orgSigned-off-by:
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- 07 Feb, 2024 3 commits
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Chen-Yu Tsai authored
The MT8192 does not support configuring pin slew rate. This is evident from both the datasheet, and the fact that the driver points the slew rate register range at the GPIO direction register range. Drop the bogus setting. Fixes: d32f38f2 ("pinctrl: mediatek: Add pinctrl driver for mt8192") Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240131071910.3950450-2-wenst@chromium.orgSigned-off-by:
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Chen-Yu Tsai authored
The MT8186 does not support configuring pin slew rate. This is evident from both the datasheet, and the fact that the driver points the slew rate register range at the GPIO direction register range. Drop the bogus setting. Fixes: 8b483bda ("pinctrl: add pinctrl driver on mt8186") Signed-off-by:
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Andy Shevchenko authored
There is no modifications are assumed for wpcm450_groups. Constify it. Signed-off-by:
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- 31 Jan, 2024 11 commits
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Lad Prabhakar authored
Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins provide expanded capabilities and are exclusive to the RZ/Five SoC. Couple of port pins have different configuration and are not identical for the complete port so introduce struct rzg2l_variable_pin_cfg to handle such cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config is then assigned in rzg2l_pinctrl_get_variable_pin_cfg(). Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins which support interrupt facility. While at define RZG2L_GPIO_PORT_PACK() using RZG2L_GPIO_PORT_SPARSE_PACK(). Update the gpio-ranges property in the RZ/Five SoC DTSI, as it must match the driver. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
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Lad Prabhakar authored
Currently we assume all the port pins are sequential ie always PX_0 to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to P28_5 which have holes in them, for example only one pin on port19 is available and that is P19_1 and not P19_0. So to handle such cases include pinmap for each port which would indicate the pin availability on each port. As the pincount can be calculated based on pinmap drop this from RZG2L_GPIO_PORT_PACK() macro. Previously we had a max of 7 pins on each port but on RZ/Five Port-20 has 8 pins, so move the single pin configuration to BIT(63). Signed-off-by:
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Lad Prabhakar authored
As the RZ/G2L pinctrl driver is extensively utilized by numerous SoCs and has experienced substantial growth, enhance code readability by incorporating FIELD_PREP_CONST/FIELD_GET macros wherever necessary. Signed-off-by:
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Geert Uytterhoeven authored
If the number of provided enum IDs in a variable width config register description does not match the expected number, the checker uses the expected number for validating the individual enum IDs. However, this may cause out-of-bounds accesses on the array holding the enum IDs, leading to bogus enum_id conflict warnings. Worse, if the bug is an incorrect bit field description (e.g. accidentally using "12" instead of "-12" for a reserved field), thousands of warnings may be printed, overflowing the kernel log buffer. Fix this by limiting the enum ID check to the number of provided enum IDs. Signed-off-by:
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Geert Uytterhoeven authored
R-Car V4H actually has two SCIF_CLK pins. The second pin provides the SCIF_CLK signal for HSCIF2 and SCIF4. Fixes: 050442ae ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Signed-off-by:
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Claudiu Beznea authored
Commit d3aaa720 ("pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups") introduced the possibility to parse pin configuration for pinmux groups. It did that by calling rzg2l_map_add_config() at the end of rzg2l_dt_subnode_to_map() and jumping to the remove_group label in case rzg2l_map_add_config() failed. But if that happens, the mutex will already be unlocked, thus this it will lead to double mutex unlock operation. To fix this move the rzg2l_map_add_config() call just after all the name argument is ready and before the mutex is locked. There is no harm in doing this, as this only parses the data from device tree that will be further processed by pinctrl core code. Fixes: d3aaa720 ("pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups") Reported-by:
Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/f8c3a3a0-7c48-4e40-8af0-ed4e9d9b049f@moroto.mountainSigned-off-by:
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Michal Simek authored
Compatible string doesn't really match with compatible string listed in the driver itself. While binding was converted from txt to yaml xlnx,zynq-pinctrl was listed as compatible string but example was using xlnx,pinctrl-zynq and also this string is used in all DTSes. xlnx,zynq-pinctrl is used only in dt binding and not present in any DT which is stable for quite a long time that's why use old compatible string and update binding document instead of starting to use unused compatible string. Fixes: 153df45a ("dt-bindings: pinctrl: pinctrl-zynq: Convert to yaml") Signed-off-by:
Michal Simek <michal.simek@amd.com> Acked-by:
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Charles Keepax authored
Use str_high_low() rather than open coding. Suggested-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by:
Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240129153138.3221604-3-ckeepax@opensource.cirrus.comSigned-off-by:
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Charles Keepax authored
Remove some pointless inline declarations, no reason not to let the compiler decide. Suggested-by:
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Charles Keepax authored
Fixup a couple of incorrect header includes. Suggested-by:
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Rob Herring authored
pincfg-node.yaml already defines the type for "slew-rate", so drop the type from the nuvoton,npcm845-pinctrl binding. Signed-off-by:
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