1. 08 Dec, 2021 7 commits
  2. 06 Dec, 2021 9 commits
  3. 23 Nov, 2021 3 commits
    • Peng Fan's avatar
      arm64: dts: imx8qxp: add cache info · ebd92296
      Peng Fan authored
      i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache
       - Icache is 2-way set associative
       - Dcache is 4-way set associative
       - L2cache is 8-way set associative
       - Line size are 64bytes
      Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
      Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
      ebd92296
    • Peng Fan's avatar
      arm64: dts: imx8qm: add cache info · b0b46118
      Peng Fan authored
      i.MX8QM A53 Cluster has 32KB Icache, 32KB Dcache and 1MB L2 Cache
        - Icache is 2-way set associative
        - Dcache is 4-way set associative
        - L2cache is 16-way set associative
        - Line size are 64bytes
      
      A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
       - ICache is 3-way set-associative
       - Dcache is 2-way set-associative
       - L2Cache is 16-way set-associative
       - Line size are 64bytes
      Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
      Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
      b0b46118
    • Peng Fan's avatar
      arm64: dts: imx8m: add cache info · cb551b5e
      Peng Fan authored
      i.MX8M Family use A53 Cores and has 32KB ICache with 32KB DCache.
       - Icache is 2-way set associative
       - Dcache is 4-way set associative
       - L2cache is 16-way set associative
       - Line size are 64bytes
      
      Except i.MX8MQ has 1MB L2 Cache, others has 512KB L2 Cache.
      
      So add the cache info in device tree and let use could see that
      from /sys/devices/system/cpu/cpu[x]/cache/
      Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
      Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
      cb551b5e
  4. 22 Nov, 2021 5 commits
  5. 21 Nov, 2021 3 commits
  6. 14 Nov, 2021 13 commits