- 16 Mar, 2018 12 commits
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Yoshihiro Shimoda authored
This patch adds support for r8a77965 (R-Car M3-N). This SoC has dedicated pins. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com>
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Yoshihiro Shimoda authored
This patch adds support for r8a77965 (R-Car M3-N). Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Amelie Delaunay authored
This patch adds phy transceiver driver for STM32 USB PHY Controller (USBPHYC) that provides dual port High-Speed phy for OTG (single port) and EHCI/OHCI host controller (two ports). One port of the phy is shared between the two USB controllers through a UTMI+ switch. [fengguang.wu@intel.com: Make stm32_usbphyc_get_pll_params() to be static] Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by:
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Amelie Delaunay authored
This patch adds the device tree bindings description for STM32 USBPHYC (USB PHY Controller). Signed-off-by:
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Masahiro Yamada authored
These configs select MFD_SYSCON, but do not depend on HAS_IOMEM. Compile testing on architecture without HAS_IOMEM causes "unmet direct dependencies" in Kconfig phase. Detected by "make ARCH=score allyesconfig". Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Martin Blumenstingl authored
This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout). Unfortunately there is no documentation for this PHY in the public S905X datasheet (published for example by Khadas). What we know so far about this PHY: - even though the Meson GXL and GXM SoCs do not expose an USB3 port (the dwc3 controller only has USB2 ports enabled) we need to initialize the USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this initialization high-speed USB devices (especially USB hard disks and thumb drives, slower devices like mice do not seem to be affected) - on some boards the USB3 PHY starts in "device mode" - we want to bring it into a known state (by switching it to host mode for now). - it is responsible for the OTG detection and for switching the first USB2 PHY between host and peripheral (aka device) mode. an interrupt can be used to detect changes between host and device mode. There are five inputs to this register area: - the clock and reset line for the USB3 PHY itself - the clock and reset line for the peripheral mode and OTG detection logic (on the GXL and GXM SoCs these are the same clock and reset line as for the USB3 PHY itself, but Amlogic sees this as two different components - even though they share the same register space - so they have to be passed individually to allow specifying different inputs on other SoCs if needed) - the interrupt for the OTG detection logic The whole OTG detection logic is not implemented yet. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:
Yixun Lan <yixun.lan@amlogic.com> Tested-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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Martin Blumenstingl authored
Amlogic Meson GXL SoCs use a dwc3 controller with two (GXM - a variant for GXL, has three) USB2 ports. The first USB2 port supports host and peripheral (also called "device") mode. While the dwc3 controller has no USB3 port enabled we still need the USB3 PHY to be initialized. Otherwise high-speed USB transfers (for example with a USB flash drive) may time out (most often seen on boards with mainline u-boot, where the bootloader does not initialize the USB3 PHY registers). Signed-off-by:
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Alexander Monakov authored
Make the value written into the USB_PHY_RX_CTRL configuration register match 0xAA79 value written by manufacturer-supplied kernels for Sony NSZ-GS7 (Berlin2 SoC), Google Chromecast and Valve Steam Link (BG2CD). This fixes timeouts communicating to the internal hub on Steam Link. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by:
Alexander Monakov <amonakov@ispras.ru> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
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Chunfeng Yun authored
Add two properties of ref_clk and coefficient used by U2 slew rate calibrate which may vary on different SoCs Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by:
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Chunfeng Yun authored
There are two parameters, ref_clk and coefficient, for U2 slew rate calibrate which may vary on different SoCs, here allow them to be configurable Signed-off-by:
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Chunfeng Yun authored
The default value of mcu_bus_ck_gate_en is 1, if clear it, will prevent system to enter deep idle mode, so keep its default value and without affecting PCIe function. Signed-off-by:
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Alexey Khoroshilov authored
If regmap_update_bits() fails in lpc18xx_usb_otg_phy_power_on(), lpc->clk is left enabled. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by:
Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by:
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- 12 Mar, 2018 1 commit
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Chen-Yu Tsai authored
The AXP223 PMIC, like the AXP221, does not generate VBUS change interrupts when N_VBUSEN is used to drive VBUS for the OTG port on the board. This was not noticed until recently, as most A23/A33 boards use a GPIO pin that does not support interrupts for OTG ID detection. This forces the driver to use polling. However the A33-OlinuXino uses a pin that does support interrupts, so the driver uses them. However the VBUS interrupt never fires, and the driver never gets to update the VBUS status. This results in musb timing out waiting for VBUS to rise. This was worked around for the AXP221 by resorting to polling changes in commit 91d96f06 ("phy-sun4i-usb: Add workaround for missing Vbus det interrupts on A31"). This patch adds the A23 and A33 to the list of SoCs that need the workaround. Fixes: fc1f45ed ("phy-sun4i-usb: Add support for the usb-phys on the sun8i-a33 SoC") Fixes: 123dfdbc ("phy-sun4i-usb: Add support for the usb-phys on the sun8i-a23 SoC") Cc: <stable@vger.kernel.org> # 4.3.x: 68dbc2ce phy-sun4i-usb: Use of_match_node to get model specific config data Cc: <stable@vger.kernel.org> # 4.3.x: 5cf700ac phy: phy-sun4i-usb: Fix optional gpios failing probe Cc: <stable@vger.kernel.org> # 4.3.x: 04e59a02 phy-sun4i-usb: Fix irq free conditions to match request conditions Cc: <stable@vger.kernel.org> # 4.3.x: 91d96f06 phy-sun4i-usb: Add workaround for missing Vbus det interrupts on A31 Cc: <stable@vger.kernel.org> # 4.3.x Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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- 08 Mar, 2018 26 commits
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Martin Blumenstingl authored
The U2P_R2 register provides "test mode" functionality for bits 17:0. These are only used during SoC development and should be left untouched on production SoC versions. Rename these register definitions to indicate that these are for "test mode" only. While here, also merge the definitions for U2P_R2_DATA_IN_MASK and U2P_R2_DATA_IN_EN_MASK (bits 0:7) because Amlogic's internal documentation suggests that these bits belong together. The old definition was not taken from the documentation but rather from a struct definition in the Amlogic GPL kernel sources. No functional changes. Suggested-by:
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Martin Blumenstingl authored
The USB2 PHY can switch between PHY_MODE_USB_HOST and PHY_MODE_USB_DEVICE. However, it cannot do it on it's own since it requires re-routing of the corresponding USB pins from dwc3 (which is used for host-mode) to dwc2 (which is used for device-mode). Thus we don't need to auto-detect the mode based on the USB controller, which simplifies the driver code. Signed-off-by:
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Martin Blumenstingl authored
The Meson GXL USB2 PHYs require an additional clock (USB) which has to be enabled. If that clock is disabled then all PHY registers read 0x0. Luckily for us that clock is always enabled (either by harddware defaults, the bootrom, or any of the bootloaders before u-boot/BL3-3). The OTG capable USB2 PHY additionally has a reset line (USB_OTG, which is shared with other components, such as the USB3 PHY for example). Extend the driver so it handles this clock and the shared reset line. We only trigger the reset during the .init phase since it's a shared reset line, so triggering it during the driver's .reset implementation would effectively also only trigger it once anyways. Signed-off-by:
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Martin Blumenstingl authored
devm_phy_create can return -EPROBE_DEFER if the phy-supply is not ready yet. Silence this warning as the driver framework will re-attempt registering the PHY - this second try works without any errors. So only log actual errors to keep the kernel log free of misleading error messages. Signed-off-by:
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Martin Blumenstingl authored
The OTG capable USB2 PHY has a reset line (which is shared with other components, such as the USB3 PHY for example) and a clock (which are both part of different registers). Add the properties for the reset line and clocks as optional ones since not all PHYs have them (currently only the OTG capable PHY is known to use these). Signed-off-by:
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Dov Levenglick authored
Add missing documentation of structure members and modify the order of documentation to match that of the structure declaration. Signed-off-by:
Dov Levenglick <dov.levenglick@gmail.com> Signed-off-by:
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Shawn Lin authored
Just use the API instead of open-coding it, no functional change intended. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by:
Brian Norris <briannorris@chromium.org> Signed-off-by:
Caesar Wang <wxt@rock-chips.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Shawn Lin authored
It turns out that 5us isn't enough for all cases, so let's retry some more times to wait for caldone. Signed-off-by:
Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by:
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Ulf Magnusson authored
Exynos4212 support was removed by commit bca9085e ("ARM: dts: exynos: remove Exynos4212 support (dead code)"). Remove the SOC_EXYNOS4212 dependency from PHY_EXYNOS4X12_USB. Discovered with the https://github.com/ulfalizer/Kconfiglib/blob/master/examples/list_undefined.py script. Signed-off-by:
Ulf Magnusson <ulfalizer@gmail.com> Acked-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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Manu Gautam authored
The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. Signed-off-by:
Manu Gautam <mgautam@codeaurora.org> Signed-off-by:
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Manu Gautam authored
Disable clocks and enable PHY autonomous mode to detect wakeup events when PHY is suspended. Core driver should notify speed to PHY driver to enable LFPS and/or RX_DET interrupts. Signed-off-by:
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Manu Gautam authored
Disable clocks and enable DP/DM wakeup interrupts when suspending PHY. Core driver should notify speed to PHY driver to enable appropriate DP/DM wakeup interrupts polarity in suspend state. Signed-off-by:
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Manu Gautam authored
Add following USB speed related PHY modes: LS (Low Speed), FS (Full Speed), HS (High Speed), SS (Super Speed) Speed related information is required by some QCOM PHY drivers to program PHY monitor resume/remote-wakeup events in suspended state. Speed is needed in order to set correct polarity of wakeup events for detection. E.g. QUSB2 PHY monitors DP/DM line state depending on whether speed is LS or FS/HS to detect resume. Similarly QMP USB3 PHY in SS mode should monitor RX terminations attach/detach and LFPS events depending on SSPHY is active or not. Signed-off-by:
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Manu Gautam authored
QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY with dual RX/TX lanes to support type-c. There is a separate block DP_COM for configuration related to type-c or DP. Add support for dp_com region and secondary rx/tx lanes initialization. Signed-off-by:
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Manu Gautam authored
Update compatible string and clock names for QMP version V3 USB PHY. Acked-by:
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Manu Gautam authored
Registers offsets for QMP V3 PHY are changed from previous versions (1/2), update same in header file. Signed-off-by:
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Manu Gautam authored
New revision (v3) of QMP PHY uses different offsets for almost all of the registers. Hence, move these definitions to header file so that updated offsets can be added for QMP v3. Signed-off-by:
Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by:
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Manu Gautam authored
Use register layout to add additional registers present on QUSB2 PHY V2 version for PHY initialization. Other than new registers on V2, following two register's offset and bit definitions are different: POWERDOWN control and PLL_STATUS. Signed-off-by:
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Manu Gautam authored
Update generic compatible string for QUSB2 V2 PHY. This will allow all targets using QUSB2 V2 use same string. Acked-by:
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Manu Gautam authored
New version of QUSB2 PHY has some registers offset changed. Add support to have register layout for a target and update the same in phy_configuration. Signed-off-by:
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Manu Gautam authored
Driver is currently performing PHY reset after starting SERDES/PCS. As per hardware datasheet reset must be done before starting PHY. Hence, update the sequence. Signed-off-by:
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Manu Gautam authored
PHY block or asynchronous reset requires signal to be asserted before de-asserting. Driver is only de-asserting signal which is already low, hence reset operation is a no-op. Fix this by asserting signal first. Also, resetting requires PHY clocks to be turned ON only after reset is finished. Fix that as well. Signed-off-by:
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Manu Gautam authored
PHY must be powered on before turning ON clocks and attempting to initialize it. Driver is exposing separate init and power_on routines for this. Apparently USB dwc3 core driver performs power-on after init. Also, poweron and init for QUSB2 PHY need to be executed together always, hence remove poweron callback from phy_ops and explicitly perform this from init, similar changes needed for poweroff. Signed-off-by:
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Manu Gautam authored
PHY regulators which are enabled from power_on() must be ON before turning-on clocks and initializing it as part of init(). As most of the core drivers perform power_on() after init(), move PHY regulators enable to com_init() and use power_on() to only enable pipe_clk. This pipe_clk is output from PHY and some core drivers e.g. PCIe follow specific sequence after phy_init() that mandates pipe_clk to be enabled from power_on() only. On similar lines move clk_enable from init() to com_init() which executes once for multi lane PHYs. Signed-off-by:
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Vivek Gautam authored
Move from using array of clocks to clk_bulk_* APIs that are available now. Signed-off-by:
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Vivek Gautam authored
Pipe clock comes out of the phy and is available as long as the phy is turned on. Clock controller fails to gate this clock after the phy is turned off and generates a warning. / # [ 33.048561] gcc_usb3_phy_pipe_clk status stuck at 'on' [ 33.048585] ------------[ cut here ]------------ [ 33.052621] WARNING: CPU: 1 PID: 18 at ../drivers/clk/qcom/clk-branch.c:97 clk_branch_wait+0xf0/0x108 [ 33.057384] Modules linked in: [ 33.066497] CPU: 1 PID: 18 Comm: kworker/1:0 Tainted: G W 4.12.0-rc7-00024-gfe926e34c36d-dirty #96 [ 33.069451] Hardware name: Qualcomm Technologies, Inc. DB820c (DT) ... [ 33.278565] [<ffff00000849b27c>] clk_branch_wait+0xf0/0x108 [ 33.286375] [<ffff00000849b2f4>] clk_branch2_disable+0x28/0x34 [ 33.291761] [<ffff0000084868dc>] clk_core_disable+0x5c/0x88 [ 33.297660] [<ffff000008487d68>] clk_core_disable_lock+0x20/0x34 [ 33.303129] [<ffff000008487d98>] clk_disable+0x1c/0x24 [ 33.309384] [<ffff0000083ccd78>] qcom_qmp_phy_poweroff+0x20/0x48 [ 33.314328] [<ffff0000083c53f4>] phy_power_off+0x80/0xdc [ 33.320492] [<ffff00000875c950>] dwc3_core_exit+0x94/0xa0 [ 33.325784] [<ffff00000875c9ac>] dwc3_suspend_common+0x50/0x60 [ 33.331080] [<ffff00000875ca04>] dwc3_runtime_suspend+0x48/0x6c [ 33.336810] [<ffff0000085b82f4>] pm_generic_runtime_suspend+0x28/0x38 [ 33.342627] [<ffff0000085bace0>] __rpm_callback+0x150/0x254 [ 33.349222] [<ffff0000085bae08>] rpm_callback+0x24/0x78 [ 33.354604] [<ffff0000085b9fd8>] rpm_suspend+0xe0/0x4e4 [ 33.359813] [<ffff0000085bb784>] pm_runtime_work+0xdc/0xf0 [ 33.365028] [<ffff0000080d7b30>] process_one_work+0x12c/0x28c [ 33.370576] [<ffff0000080d7ce8>] worker_thread+0x58/0x3b8 [ 33.376393] [<ffff0000080dd4a8>] kthread+0x100/0x12c [ 33.381776] [<ffff0000080836c0>] ret_from_fork+0x10/0x50 Fix this by disabling it as the first thing in phy_exit(). Fixes: e78f3d15 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Signed-off-by:
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- 21 Feb, 2018 1 commit
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Jianguo Sun authored
Add combo phy driver for HiSilicon STB SoCs. This phy can be used as pcie-phy, sata-phy or usb-phy. Changes for v5: - Add bindings doc for Hi3798CV200 peripheral controller, and refer to the bindings of this parent node in combphy bindings doc. Changes for v4: - Instead of relying on device id, add a new property hisilicon,fixed-mode for combphy device that doesn't support mode select but a fixed phy mode. - Move combphy mode select register bits definition to device tree, as it may vary from one device to another. Changes for v3: - Make combphy device be child of peripheral controller and use 'reg' property for mapping combphy configuration registers. - Kill "hisilicon,peripheral-syscon" property, since parent node is just the syscon controller now. - Check combphy id to handle the quirk that combphy0 can not configure mode but always works in USB3 mode. - Unify phy .init and .exit hooks for different combphy instances and work modes, as the only quirk we need to handle is that combphy0 can only work in USB3 mode. - Better naming for clock and reset, 'ref' to 'ref_clk', 'por' to 'por_rst'. Changes for v2: - Move DT bindings into a separate patch. - Drop the spurious newline from drivers/phy/Makefile. - Use the phy type defines in dt-bindings/phy/phy.h. - Use PTR_ERR_OR_ZERO() for checking return from devm_of_phy_provider_register(). - Add USB3 phy support. Signed-off-by:
Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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