- 13 Sep, 2018 40 commits
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Hoan Nguyen An authored
The r8a77965 has a single FDP1 instance. Signed-off-by:
Hoan Nguyen An <na-hoan@jinso.co.jp> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
- Device nodes with unit addresses are sorted by unit address, - Device nodes without unit addresses and references are sorted alphabetically. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Wolfram Sang authored
Successfully tested on H3 ES1.0 and ES2.0, M3-W ES1.0, and M3-N ES1.0. Even previously stubborn cards work fine. Transfer rates were >60MB/s. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Takeshi Kihara authored
This patch adds SYS-DMAC{0,1,2} device nodes for the R8A77990 SoC. Signed-off-by:Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Yoshihiro Kaneko <ykaneko0929@gmail.com> Reviewed-by:
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Takeshi Kihara authored
Add device nodes for I2C ch[0-7] to R-Car E3 R8A77990 device tree. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by:
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Koji Matsuoka authored
Add device nodes for VIN4, VIN5 and CSI40 to R-Car E3 R8A77990 device tree. Signed-off-by:
Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by:
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Geert Uytterhoeven authored
Add the device nodes for all MSIOF SPI controllers, incl. clocks, power domains, and resets properties. Signed-off-by:
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Geert Uytterhoeven authored
To preserve by-address-per-group sort order. Fixes: 0f6d237c ("arm64: dts: renesas: r8a7795: add ccree to device tree") Signed-off-by:
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Takeshi Kihara authored
Add the device node for the external SCIF_CLK, and describe the clock inputs for the Baud Rate Generator for External Clock (BRG) for SCIF2, which can increase serial clock accuracy. The presence of the SCIF_CLK crystal and its clock frequency depend on the actual board. Signed-off-by:
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Geert Uytterhoeven authored
Use the SoC-specific CPG/MSSR include file to allow future use of R8A77990_CLK_* symbols. Replace the hardcoded power domain indices by R8A77990_PD_* symbols. Signed-off-by:
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Geert Uytterhoeven authored
The comments describing the non-default switch settings to use SATA are confusing: 'Off' refers to the switch position, not to the MD12 logic value, while the parentheses suggest otherwise. Rephrase to fix this. Fixes: bec000784d5bb571 ("arm64: dts: renesas: salvator-xs: enable SATA") Signed-off-by: -
Geert Uytterhoeven authored
usb2_phy1 accidentally uses the same clock/reset as usb2_phy0. Fixes: b5857630 ("arm64: dts: renesas: r8a77965: add usb2_phy nodes") Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
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Geert Uytterhoeven authored
Should be "renesas,usbhs-r8a77965", not "renesas,usbhs-r8a7796". Fixes: a06e8af8 ("arm64: dts: renesas: r8a77965: add HS-USB node") Signed-off-by:
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Geert Uytterhoeven authored
To preserve alphabetical sort order. Fixes: 4c529600 ("arm64: dts: renesas: r8a77965: Add R-Car Gen3 thermal support") Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by:
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Geert Uytterhoeven authored
To preserve alphabetical sort order. Fixes: 4edac426aff11a37 ("arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support") Signed-off-by: -
Geert Uytterhoeven authored
Signed-off-by:
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Eugeniu Rosca authored
This is based on the existing KF device tree sources: $ ls -1 arch/arm64/boot/dts/renesas/*-kf.dts arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts Signed-off-by:
Eugeniu Rosca <erosca@de.adit-jv.com> Signed-off-by:
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Sergei Shtylyov authored
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor board. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device tree. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
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Biju Das authored
Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
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Biju Das authored
Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi. Signed-off-by:
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Biju Das authored
Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi. Signed-off-by:
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Fabrizio Castro authored
Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly to what was done for the r8a7796 with commit 41dbbf0c ("arm64: dts: r8a7796: Add FCPF and FCPV instances"), commit 69490bc9 ("arm64: dts: renesas: r8a7796: Point FDP1 via FCPF to IPMMU-VI0"), and commit cef942d0 ("arm64: dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0"). Signed-off-by:
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Biju Das authored
Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1). This work is based on similar work done on the R8A7796 SoC by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>. Signed-off-by:
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Fabrizio Castro authored
This patch adds PWM[0123456] device nodes to the RZ/G2M (a.k.a R8A774A1) device tree. Signed-off-by:
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Biju Das authored
This patch adds definitions for L2 cache for the Cortex-A53 CPU cores (512 KiB in size, organized as 32 KiB x 16 ways), adds Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57 + 4 x Cortex-A53), and finally enables the performance monitor unit for the Cortex-A53 cores on the R8A774A1 SoC. Based on work done for r8a7796 SoC. Signed-off-by:
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Biju Das authored
Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC. Based on several similar patches of the R8A7796 device tree by Geert Uytterhoeven <geert+renesas@glider.be> and Simon Horman <horms+renesas@verge.net.au>. Signed-off-by:
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Fabrizio Castro authored
Add r8a774a1 IPMMU nodes. Signed-off-by:
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Biju Das authored
Add thermal support for R8A774A1 (RZ/G2M) SoC. Based on the work done for r8a7796 SoC. Signed-off-by:
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Biju Das authored
Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS) devices nodes to the r8a774a1 device tree. Signed-off-by:
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Fabrizio Castro authored
Add SDHI nodes to the DT of the r8a774a1 SoC. Signed-off-by:
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Fabrizio Castro authored
Add GPIO device nodes to the DT of the r8a774a1 SoC. Signed-off-by:
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Fabrizio Castro authored
This patch adds pinctrl device node for R8A774A1 SoC. Signed-off-by:
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Biju Das authored
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas RZ/G2M (r8a774a1) SoC. Signed-off-by:
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Fabrizio Castro authored
This patch adds the SoC specific part of the Ethernet AVB device tree node. Signed-off-by:
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Biju Das authored
Add support for the Interrupt Controller for External Devices (INTC-EX) on RZ/G2M. Signed-off-by:
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Fabrizio Castro authored
Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports, incl. clocks, power domains and DMAs. According to the HW user manual, SCIF[015] and HSCIF[012] are connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and HSCIF[34] are connected to SYS-DMAC0. Signed-off-by:
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Biju Das authored
Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC. Signed-off-by:
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Sergei Shtylyov authored
Define the Condor/V3HSK board dependent parts of the DU and LVDS device nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and Analog Devices ADV7511W HDMI transmitter... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by:
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Sergei Shtylyov authored
Add the eMMC chip support for the V3M Started Kit board. Based on the original (and large) patches by Vladimir Barinov. Signed-off-by:
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