- 30 Mar, 2017 40 commits
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Christian König authored
v2: new approach fixing this by registering a fence callback for all users of the VM on teardown v3: agd: rebase Signed-off-by:Christian König <christian.koenig@amd.com> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Don't assume kmalloc will always succeed. v2: agd: rebase Signed-off-by:
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Christian König authored
When two VMs stop using PRT support at the same time we might not disable it in the right order otherwise. v2: agd: rebase Signed-off-by:
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Alex Xie authored
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Alex Xie <AlexBin.Xie@amd.com> Signed-off-by:
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Christian König authored
Those should be 64bit, even on a 32bit system. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Tom St Denis authored
This update allows sensors to return more than 1 value and indicates to the caller how many bytes are written. The debugfs interface has been updated to handle reading all of the values. Simply seek to the enum value (multiplied by 4) and then read as many bytes as the sensor provides. (v2): Don't set size to 4 before reading GPU_POWER (v3): agd: rebase Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Christian König authored
Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: set correct register Signed-off-by:
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Christian König authored
Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: set correct register Signed-off-by:
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Christian König authored
Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: write to the correct register, adjust bits to that hw generation v3: fix compilation, add the missing register bit definitions Signed-off-by:
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Junwei Zhang authored
Till GFX8 we can only enable PRT support globally, but with the next hardware generation we can do this on a per page basis. Keep the interface consistent by adding PRT mappings and enable support globally on current hardware when the first mapping is made. v2: disable PRT support delayed and on all error paths v3: PRT and other permissions are mutal exclusive, PRT mappings don't need a BO. v4: update PRT mappings durign CS as well, make va_flags 64bit Signed-off-by: -
Christian König authored
Future hardware generations can handle PRT flags on a per page basis, but current hardware can only turn it on globally. Add the basic handling for both, a global callback to enable/disable triggered by setting a per mapping flag. v2: agd: rebase fixes Signed-off-by:
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Christian König authored
For PRT support we need mappings which aren't backed by any memory. v2: fix parameter checking Signed-off-by:
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Monk Liu authored
no suspend invoked so after VF FLR by host, we just call hw_init to reinitialize IPs. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com Signed-off-by:
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Eric Huang authored
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Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Eric Huang authored
The additional output are: vddc power in Watt; vddci power in Watt; max gpu power in Watt; average gpu power in Watt. Signed-off-by:
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Eric Huang authored
As well as fix print format for uint32_t type. Signed-off-by:
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Eric Huang authored
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Rex Zhu <Rex.Zhu@amd.com> Acked-by:
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Eric Huang authored
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Eric Huang authored
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Eric Huang authored
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Eric Huang authored
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Eric Huang authored
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Eric Huang authored
Add the sysfs entries pp_gfx_power_profile and pp_compute_power_profile which give user a way to set power profile through parameters minimum sclk, minimum mclk, activity threshold, up hysteresis and down hysteresis only when the entry power_dpm_force_performance_level is in default value "auto". It is read and write. Example: echo 500 800 20 0 5 > /sys/class/drm/card0/device/pp_*_power_profile cat /sys/class/drm/card0/device/pp_*_power_profile 500 800 20 0 5 Note: first parameter is sclk in MHz, second is mclk in MHz, third is activity threshold in percentage, fourth is up hysteresis in ms and fifth is down hysteresis in ms. echo set > /sys/class/drm/card0/device/pp_*_power_profile To set power profile state if it exists. echo reset > /sys/class/drm/card0/device/pp_*_power_profile To restore default state and clear previous setting. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
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Monk Liu authored
this lock is used for sriov_gpu_reset, only get this mutex can run into sriov_gpu_reset. we have couple source triggers gpu_reset for SRIOV: 1) submit timedout and trigger reset voluntarily 2) invalid instruction detected by ENGINE and trigger reset voluntarily 2) hypervisor found world switch hang and trigger flr and notify guest to do reset. all need take care and we need a mutex to protect the consistency of reset routine. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
implement SRIOV gpu_reset for future use. it wil be called from: 1) job timeout 2) privl access or instruction error interrupt 3) hypervisor detect VF hang v2: agd: rebase on upstream Signed-off-by:
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Monk Liu authored
sw part only invoked once during sw_init. hw part invoked during first drv load and resume later. that way we cannot alloc mqd in hw/resume, we only keep mqd allocted in sw_init routine. and hw_init routine only kmap and set it. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
We ultimately want to re-use this for bare metal, so no need to have vf checks in the KIQ code itself since kiq itself is currently only used in VF cases. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
this is for SRIOV fix: mqd soft init/fini will be invoked by sw_init to allocate BO for compute MQD resource, instead of original scheme that hw_init allocates MQD. because if hw_init allocates MQD, then resume will allocate MQD, and that lead to memory leak after driver recovered from hang. Signed-off-by:
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Monk Liu authored
introduce a new mqd member in ring is for later usage. we need keep a clean version of MQD for the purpose of recovering compute rings from hang. Signed-off-by:
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Monk Liu authored
CG & PG function changes engine clock/gating, which is not appropriate for VF device, because one vf doesn't know the whole picture of engine's overall workload. Signed-off-by:
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Pixel Ding authored
CPU is not efficient to clean framebuffer especially under virtualization, then loading driver takes long time which causes timeout of mailbox handshake. Signed-off-by:
Pixel Ding <Pixel.Ding@amd.com> Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by:
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Monk Liu authored
ib_pool init should prior to fbdev_init, otherwise there will be error from amdgpu_sa_bo_new (amdgpu_sa.c:323) fbdev_init will call ttm_validate which further call amdgpu_sa_bo_new. v2: move fbdev_init behind ib test. Signed-off-by:
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Pixel Ding authored
VF uses KIQ to access registers. When VM fault occurs, the driver can't get back the fence of KIQ submission and runs into CPU soft lockup. Signed-off-by:
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Pixel Ding authored
When multiple VFs try to enter exclusive mode at the same time, the looping mechansim doesn't help to ensure each can get it because it only loops active VFs, then the last one has to wait for a long interval. Signed-off-by:
Xiangliang.Yu <Xiangliang.Yu@amd.com> Signed-off-by:
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Monk Liu authored
1,like pp_hw_init, we shouldn't report error if PP disabled 2,disable pp_en if sriov Signed-off-by:
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