- 15 May, 2018 24 commits
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Rex Zhu authored
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Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Shirish S authored
is_blanked() hook is a dummy one for underlay pipe, hence when called, it loops for ~300ms at boot. This patch removes this dummy call and adds missing checks. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Harry Wentland authored
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Leo (Sunpeng) Li <sunpeng.li@amd.com> Signed-off-by:
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Harry Wentland authored
We enabled this upstream by default now and no longer need the flag. Signed-off-by:
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Harry Wentland authored
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Christian König authored
The detection if a BO was placed in CPU visible VRAM was incorrect. Fix it and merge it with the correct detection in amdgpu_ttm.c Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
Instead of the global (inaccurate) counter. Signed-off-by:
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Evan Quan authored
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Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
pp_soc15.h is vega10 specific. Update powerplay code to use soc15 common macros defined in soc15_common.h. Signed-off-by:
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Evan Quan authored
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Rex Zhu authored
In order to share pp_atomfwctrl_get_vbios_bootup_values on asics with different BIOS_CLKID. Not call function pp_atomfwctrl_get_clk_information_by_clkid in pp_atomfwctrl_get_vbios_bootup_values. Reviewed-by:
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Huang Rui authored
When system uses fw direct loading, then psp context structure won't be initiliazed. And it is also unable to execute mode reset. [ 434.601474] amdgpu 0000:0c:00.0: GPU reset begin! [ 434.694326] amdgpu 0000:0c:00.0: GPU reset [ 434.743152] BUG: unable to handle kernel NULL pointer dereference at 0000000000000058 [ 434.838474] IP: psp_gpu_reset+0xc/0x30 [amdgpu] [ 434.893532] PGD 406ed9067 [ 434.893533] P4D 406ed9067 [ 434.926376] PUD 400b46067 [ 434.959217] PMD 0 [ 435.033379] Oops: 0000 [#1] SMP [ 435.072573] Modules linked in: amdgpu(OE) chash(OE) gpu_sched(OE) ttm(OE) drm_kms_helper(OE) drm(OE) fb_sys_fops syscopyarea sysfillrect sysimgblt rpcsec_gss_krb5 auth_rpcgss nfsv4 nfs lockd grace fscache snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm edac_mce_amd snd_seq_midi snd_seq_midi_event kvm_amd snd_rawmidi kvm irqbypass crct10dif_pclmul crc32_pclmul snd_seq ghash_clmulni_intel snd_seq_device pcbc snd_timer eeepc_wmi aesni_intel snd asus_wmi aes_x86_64 sparse_keymap crypto_simd glue_helper joydev soundcore wmi_bmof cryptd video i2c_piix4 shpchp 8250_dw i2c_designware_platform mac_hid i2c_designware_core sunrpc parport_pc ppdev lp parport autofs4 hid_generic igb usbhid dca ptp mxm_wmi pps_core ahci hid i2c_algo_bit [ 435.931754] libahci wmi Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Nico Sneck authored
With this the dGPU turns on correctly. Signed-off-by:
Nico Sneck <nicosneck@hotmail.com> Signed-off-by:
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Leo (Sunpeng) Li authored
Input transfer function creation is now done when the plane is created. This is done within the following change: Author: Anthony Koo <Anthony.Koo@amd.com> drm/amd/display: Have DC manage its own allocation of gamma Therefore, we no longer need to create it when filling in the plane attributes. Signed-off-by: -
Leo (Sunpeng) Li authored
Before programming the input gamma, check that we're not using the identity correction. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Anthony Koo authored
Creating plane will also allocate gamma and input TF Creating stream will also allocate outputTF Fix issue with gamma not applied OS may call SetGamma before surface committed, so need to store in target and apply later. Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Anthony Koo authored
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Anthony Koo authored
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Anthony Koo authored
Remove some unnecessary TF definitions from update structures Signed-off-by:
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Anthony Koo authored
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Anthony Koo authored
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Anthony Koo authored
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Anthony Koo authored
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Anthony Koo authored
Updated HDR Static Metadata to directly take info packet raw Updating Infopacket does not require Passive Signed-off-by:
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- 11 Apr, 2018 16 commits
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Roman Li authored
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Roman Li <roman.li@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Anthony Koo authored
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Eric Bernstein authored
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Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Yongqiang Sun authored
Instead of user set brightness with range of percentage, HLK test set brightness level with range of normal, this will result in HLK test case set brightness from 0 to 255, DC set brightness with ramp is 0, and disabled ramp change which will fail the HLK test. Fix: In case of unblank stream and turn on edp, change brightness level in stream to 0xFFFFFFFF(actural maximum level is 0xFF), use that value as a flag to recogonize this the case of resume from S3. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Jun Lei authored
We would otherwise fallback to the timing, which would always give us identity. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
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Eric Yang authored
Link bw required is reduced when we have chroma subsampling. Signed-off-by:
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Jun Lei authored
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Eric Bernstein authored
Move DCN1 implementation of stream encoder to new file (instead of common dce_stream_encoder.c). Cleanup code related to different implementation due to register definition differences. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Eric Yang authored
To prevent future optimization related bugs, just set all update flags when we have a full update, since we know we want to reprogram everything in that case. Signed-off-by:
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Charlene Liu authored
As per eDP 1.4 spec, there must be at least 500ms delay between eDP power off and on. This change added time stamp when edp power off, which can be used to calculate duration time when edp power on. If duration less than 500ms, add a wait. Signed-off-by:
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Harry Wentland authored
We use this to ensure we wait at least 500ms in between eDP disable/enable. Signed-off-by:
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Anthony Koo authored
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Bhawanpreet Lakha authored
Created Macros for DC_LOG_XXX to pr_debug() & DRM_DEBUG_KMS. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Harry Wentland authored
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