- 05 Dec, 2022 12 commits
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Bhupesh Sharma authored
Add compatible and constants for the power domains exposed by the SM4250 RPM. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221127112204.1486337-2-bhupesh.sharma@linaro.org
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Abel Vesa authored
Document the compatible for SM8550. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
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Abel Vesa authored
Add LLCC configuration data for SM8550 SoC. Signed-off-by:
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Abel Vesa authored
Add LLCC compatible for SM8550 SoC. Signed-off-by:
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Abel Vesa authored
The LLCC found in SM8550 supports more slice configuration knobs and HW block version has been bumped up to 4.1. Add support for the new version and make sure the new config values are programed on probe. Signed-off-by:
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Abel Vesa authored
Add the ID for the Qualcomm SM8550 SoC. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Abel Vesa authored
The RSC interrupt is issued only after the request is complete. For fire-n-forget requests, the irq-done interrupt is sent after issuing the RPMH request and for response-required request, the interrupt is triggered only after all the requests are complete. These unnecessary checks in the interrupt handler issues AHB reads from a critical path. Lets remove them and clean up error handling in rpmh_request data structures. Co-developed-by:
Lina Iyer <ilina@codeaurora.org> Signed-off-by:
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Abel Vesa authored
The SM8550 RSC has a new set of register offsets due to its version bump. So read the version from HW and use the proper register offsets based on that. Signed-off-by:
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Abel Vesa authored
Add the power domains exposed by RPMH in the Qualcomm SM8550 platform. Signed-off-by:
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Abel Vesa authored
Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm SM8550 platform. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add SoC ID table entries for MSM8956 and MSM8976 chips. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
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AngeloGioacchino Del Regno authored
Document the identifier of MSM8956/76. Signed-off-by:
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- 12 Nov, 2022 1 commit
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Richard Acayan authored
The Snapdragon 670 uses SCM as for PSCI power management. Document the appropriate compatible string for it. Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Guru Das Srinagesh <quic_gurus@quicinc.com> Signed-off-by:
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- 10 Nov, 2022 5 commits
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Maulik Shah authored
The next wakeup timer value needs to be set in always on domain timer as the arch timer interrupt can not wakeup the SoC if after the deepest CPUidle states the SoC also enters deepest low power state. To wakeup the SoC in such scenarios the earliest wakeup time is set in CONTROL_TCS and the firmware takes care of setting up its own timer in always on domain with next wakeup time. The timer wakes up the RSC and sets resources back to wake state. Signed-off-by:
Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by:
Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by:
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Maulik Shah authored
Add changes to save drv's base address for rsc. This is used to read drv's configuration such as solver mode is supported or to write into CONTROL_TCS registers. Signed-off-by:
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Maulik Shah authored
The arch timer cannot wake up the Qualcomm Technologies, Inc. (QTI) SoCs from the deeper CPUidle states. To be able to wakeup from these deeper states, another always-on timer needs to be programmed through the so called CONTROL_TCS. As the RSC is part of CPU subsystem and the corresponding APSS RSC device is attached to the cluster PM domain (through genpd), it holds the responsibility to program the always-on timer, before entering any of these deeper CPUidle states. However, programming the timer requires information about the next hrtimer wakeup for the cluster PM domain, which is currently only known by genpd. Therefore, let's share this data through a new genpd helper function, dev_pm_genpd_get_next_hrtimer(). Signed-off-by:
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Lina Iyer authored
RSC is part the CPU subsystem and powers off the CPU domains when all the CPUs and no RPMH transactions are pending from any of the drivers. The RSC needs to flush the 'sleep' and 'wake' votes that are critical for saving power when all the CPUs are in idle. Let's make RSC part of the CPU PM domains, by attaching it to the cluster power domain. Registering for PM domain notifications, RSC driver can be notified that the last CPU is powering down. When the last CPU is powering down the domain, let's flush the 'sleep' and 'wake' votes that are stored in the data buffers into the hardware and also write next wakeup in CONTROL_TCS. Signed-off-by:
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Maulik Shah authored
The change documents power-domains property for RSC device. This optional property points to corresponding PM domain node. Signed-off-by:
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- 08 Nov, 2022 1 commit
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AngeloGioacchino Del Regno authored
Like MSM8916 and some others, MSM8976 uses qcom,smd-channels and not qcom,glink-channels. Signed-off-by:
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- 07 Nov, 2022 6 commits
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Jiasheng Jiang authored
As idr_alloc() and of_property_read_string_index() can return negative numbers, it should be better to check the return value and deal with the exception. Therefore, it should be better to use goto statement to stop and return error. Fixes: 6adba21e ("soc: qcom: Add APR bus driver") Signed-off-by:
Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by:
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Melody Olvera authored
Add SoC ID table entries for the QDU1000 and QRU1000 platforms and their variants. Signed-off-by:
Melody Olvera <quic_molvera@quicinc.com> Signed-off-by:
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Melody Olvera authored
Add SoC IDs for Qualcomm QDU1000 and QRU1000 platforms and their variants. Signed-off-by:
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Melody Olvera authored
Add the power domains exposed by RPMH in the Qualcomm QDU1000 and QRU1000 platforms. Signed-off-by:
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Melody Olvera authored
Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm QDU1000 and QRU1000 platforms. Signed-off-by:
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Manikanta Pubbisetty authored
WLAN firmware uses SMP2P protocol in order to talk to the application processor (AP) in certain cases like WoW (Wake on Wireless). WLAN firmware runs on the WPSS Q6 processor (Wireless Processor SubSystem). Therefore it is required to have sub nodes pertaining to the WPSS Q6 processor and the application processor in the SMP2P node. Add WPSS Q6 (Wireless Processor SubSystem) node names to the pattern property required for WPSS Q6 processor to communicate to the application processor and vice versa over SMP2P protocol. Signed-off-by:
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> Acked-by:
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- 06 Nov, 2022 5 commits
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AngeloGioacchino Del Regno authored
Implement the support for SAW v2.3, used in at least MSM8976, MSM8956 and APQ variants and while at it also add the configuration for the MSM8976's little (a53) and big (a72) clusters cache power management. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> [Marijn: reorder struct definitions to follow high-to-low order] Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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AngeloGioacchino Del Regno authored
Add SPM AVS Wrapper 2 compatibles for MSM8976's L2 cache. Signed-off-by:
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Luca Weiss authored
The function platform_get_irq prints an error message into the kernel log when the irq isn't found. Since the interrupt is actually optional and not provided by some SoCs, use platform_get_irq_optional which does not print an error message. Fixes: c081f306 ("soc: qcom: Add support to register LLCC EDAC driver") Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Signed-off-by:
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Vincent Knecht authored
Add SPM register information and initialization values for QCOM MSM8939 SoC. Signed-off-by:
Vincent Knecht <vincent.knecht@mailoo.org> Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
Stephan Gerhold <stephan@gerhold.net> Signed-off-by:
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Vincent Knecht authored
Document the "qcom,msm8939-saw2-v3.0-cpu" compatible for the CPU Subsystem Power Manager (SPM) on the MSM8939 SoC. Signed-off-by:
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- 17 Oct, 2022 10 commits
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Luca Weiss authored
Document the aoss-qmp compatible for sc8280xp. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
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Konrad Dybcio authored
Document the compatible for Qualcomm SM6375 SCM. SCM consumes a single clock (core / RPM_SMD_CE1_CLK), though it does not matter whether Linux enables it, as one of the billion levels of firmware ensures it's on anyway. Still, mark it as used for the sake of correctness. Signed-off-by:
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Stephen Boyd authored
This driver purely exposes information from memory to the kernel. Let's mark it as not having any device PM functionality, so that during suspend we skip even trying to call a suspend function on this device. This clears up suspend logs more than anything else, but it also shaves a few cycles off suspend. Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Stephen Boyd authored
This driver purely exposes information from memory to the kernel. Let's mark it as not having any device PM functionality, so that during suspend we skip even trying to call a suspend function on this device. This clears up suspend logs more than anything else, but it also shaves a few cycles off suspend. Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Luca Weiss authored
Add more IDs that are found in the downstream msm-4.19 kernel under the path include/linux/qpnp/qpnp-revid.h. Signed-off-by:
Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by:
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Luca Weiss authored
There are some IDs that are written in uppercase. For consistency convert them to lowercase. Signed-off-by:
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Jeff Johnson authored
Commit ff6d3658 ("soc: qcom: qmi: use const for struct qmi_elem_info") allows QMI message encoding/decoding rules to be const, so do that for QCOM PDR. Signed-off-by:
Jeff Johnson <quic_jjohnson@quicinc.com> Reviewed-by:
Alex Elder <elder@linaro.org> Reviewed-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
In some cases the hardware that the bootloader has left configured depends on RPMH power domains for their operation up until the point where the related Linux device driver probes and can inherit that configuration, or power down the hardware gracefully. Unfortunately as Linux probes the releavant drivers in sequence there are periods during the Linux boot flow where either the genpd refcount will reach 0, or worse where the active performance_state votes does not meet the requirements of the state that the hardware was left in. One specific example of this is during boot of e.g. SM8150/SC8180X, where the display clock controller probes, without any particular performance state needs (to access its registers). This will drop the MMCX rail to MIN_SVS, which isn't sufficient to sustain the clock rates that the later probing MDP is configured to. This results in an unrecoverable system state. Handle both these cases by keeping the RPMH power-domais that are referenced voted for highest state, until sync_state indicates that all devices referencing the RPMH power-domain driver has been probed. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Caleb Connolly <caleb@connolly.tech> Reviewed-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by:
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Konrad Dybcio authored
Add a compatible for the SM6375 SoC. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Konrad Dybcio authored
Document the compatible for SM6375. Signed-off-by:
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