- 29 Aug, 2019 3 commits
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Ido Schimmel authored
The new version supports extended error reporting from firmware via a new TLV in the EMAD packet. Similar to netlink extended ack. It also fixes an issue in the PCI code that can result in false AER errors under high Tx rate. Signed-off-by:
Ido Schimmel <idosch@mellanox.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Shalom Toledo authored
After 50G-1-lane and 100G-2-lanes link modes were introduced, the driver is facing situations in which the hardware auto negotiates not only on speed and type, but also on number of lanes. Prevent auto negotiation on number of lanes by allowing only port speeds that can be supported on a given port according to its width. Signed-off-by:
Shalom Toledo <shalomt@mellanox.com> Acked-by:
Jiri Pirko <jiri@mellanox.com> Signed-off-by:
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Amit Cohen authored
Commit 275e928f ("mlxsw: spectrum: Prevent force of 56G") prevented the driver from setting a speed of 56G when auto-negotiation is off. This is the only speed supported by mlxsw that cannot be set when auto-negotiation is off, which makes it difficult to write generic tests. Further, the speed is not supported by newer ASICs such as Spectrum-2 and to the best of our knowledge it is not used by current users. Therefore, remove 56G support from mlxsw. Signed-off-by:
Amit Cohen <amitc@mellanox.com> Signed-off-by:
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- 28 Aug, 2019 37 commits
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Jian Shen authored
Some ethernet drivers may call phy_start() and phy_stop() from ndo_open() and ndo_close() respectively. When network cable is unconnected, and operate like below: step 1: ifconfig ethX up -> ndo_open -> phy_start ->start autoneg, and phy is no link. step 2: ifconfig ethX down -> ndo_close -> phy_stop -> just stop phy state machine. This patch forces phy suspend even phydev->link is off. Signed-off-by:
Jian Shen <shenjian15@huawei.com> Reviewed-by:
Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queueDavid S. Miller authored
Jeff Kirsher says: ==================== 100GbE Intel Wired LAN Driver Updates 2019-08-26 This series contains updates to ice driver only. Usha fixes the statistics reported on 4 port NICs which were reporting the incorrect statistics due to using the incorrect port identifier. Victor fixes an issue when trying to traverse to the first node of a requested layer by adding a sibling head pointer for each layer per traffic class. Anirudh cleans up the locking and logic for enabling and disabling VSI's to make it more consistent. Updates the driver to do dynamic allocation of queue management bitmaps and arrays, rather than statically allocating them which consumes more memory than required. Refactor the logic in ice_ena_msix_range() for clarity and add additional checks for when requested resources exceed what is available. Jesse updates the debugging print statements to make it more useful when dealing with link and PHY related issues. Krzysztof adds a local variable to the VSI rebuild path to improve readability. Akeem limits the reporting of MDD events from VFs so that the kernel log is not clogged up with MDD events which are duplicate or potentially false positives. Fixed a reset issue that would result in the system getting into a state that could only be resolved by a reboot by testing if the VF is in a disabled state during a reset. Michal adds a check to avoid trying to access memory that has not be allocated by checking the number of queue pairs. Jake fixes a static analysis warning due to a cast of a u8 to unsigned long, so just update ice_is_tc_ena() to take a unsigned long so that a cast is not necessary. Colin Ian King fixes a potential infinite loop where a u8 is being compared to an int. Maciej refactors the queue handling functions that work on queue arrays so that the logic can be done for a single queue. Paul adds support for VFs to enable and disable single queues. Henry fixed the order of operations in ice_remove() which was trying to use adminq operations that were already disabled. ==================== Signed-off-by: -
YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
Ray Jui <ray.jui@broadcom.com> Signed-off-by:
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Colin Ian King authored
Variable result is being assigned a value that is never read and result is being re-assigned a little later on. The assignment is redundant and hence can be removed. Addresses-Coverity: ("Ununsed value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Eric Dumazet authored
Remove two holes on 64bit arches, to bring the size to one cache line exactly. Signed-off-by:
Eric Dumazet <edumazet@google.com> Signed-off-by:
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David S. Miller authored
Voon Weifeng says: ==================== stmmac: Add EHL and TGL PCI info and PCI ID In order to keep PCI info simple and neat, this patch series have introduced a 3 hierarchy of struct. First layer will be the intel_mgbe_common_data struct which keeps all Intel common configuration. Second layer will be xxx_common_data which keeps all the different Intel microarchitecture, e.g tgl, ehl. The third layer will be configuration that tied to the PCI ID only based on speed and RGMII/SGMII interface. EHL and TGL will also having a higher system clock which is 200Mhz. ==================== Signed-off-by: -
Voon Weifeng authored
EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk, ptp clock and ptp_max_adj to 200MHz. Signed-off-by:
Voon Weifeng <weifeng.voon@intel.com> Signed-off-by:
Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by:
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Voon Weifeng authored
Added EHL RGMII 1Gbps PCI ID. Different MII and speed will have different PCI ID. Signed-off-by:
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Voon Weifeng authored
Added TGL SGMII 1Gbps PCI ID. Different MII and speed will have different PCI ID. Signed-off-by:
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Voon Weifeng authored
Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have different PCI ID. Signed-off-by:
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David S. Miller authored
Marek Behún says: ==================== net: dsa: mv88e6xxx: Peridot/Topaz SERDES changes this is the fifth version of changes for the Topaz/Peridot family of switches. The patches apply on net-next. Changes since v4: - added Reviewed-by and Tested-by tags on first 2 patches, the others are changed are affected by changes in patch 3/6, so I did not add the tags, except for 5/6, which is just macro renaming - patch 3 was changed: the serdes_get_lane returns 0 on success (lane was discovered), -ENODEV if not lane is present on the port, and other error if other error occured. Lane is put into a pointer of type u8 - patches 4 and 6 were affected by this (error detecting from serdes_get_lane) - Andrew's complaint about the two additional parameters (allow_over_2500 and make_cmode_writable) was addressed, by Vivien's advice: I put a new method into chip operations structure, named port_set_cmode_writable. This is called from mv88e6xxx_port_setup_mac just before port_set_cmode. The method is implemented for Topaz. The check if cmodes over 2500 should be allowed on given port is now done in the specific port_set_cmode() that requires it, thus the allow_over_2500 argument is not needed Again, tested on Turris Mox with Peridot, Topaz, and Peridot + Topaz. ==================== Signed-off-by: -
Marek Behún authored
Currently we support SERDES on the Topaz family in a limited way: no IRQs and the cmode is not writable, thus the mode is determined by strapping pins. Marvell's examples though show how to make cmode writable on port 5 and support SGMII autonegotiation. It is done by writing hidden registers, for which we already have code. This patch adds support for making the cmode for the SERDES port writable on the Topaz family, via a new chip operation, .port_set_cmode_writable, which is called from mv88e6xxx_port_setup_mac just before .port_set_cmode. SERDES IRQs are also enabled for Topaz. Tested on Turris Mox. Signed-off-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Marek Behún authored
This is a cosmetic update. We are removing the last underscore from macros MV88E6XXX_PORT_STS_CMODE_100BASE_X and MV88E6XXX_PORT_STS_CMODE_1000BASE_X. The 2500base-x version does not have that underscore. Also PHY_INTERFACE_MODE_ macros do not have it there. Signed-off-by:
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Marek Behún authored
By adding an additional serdes_get_lane implementation (for Topaz), we can merge the implementations of other SERDES functions (powering and IRQs). We can skip checking port numbers, since the serdes_get_lane() methods inform if there is no lane on a port or if the lane cannot be used for given cmode. Signed-off-by:
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Marek Behún authored
Create a serdes_get_lane() method in the mv88e6xxx operations structure. Use it instead of calling the different implementations. Also change the methods so that their return value is used only for error. The lane number is put into a place referred to by a pointer given as argument. If the port does not have a lane, return -ENODEV. Lanes are phy addresses, so use u8 as their type. Signed-off-by:
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Marek Behún authored
This patch moves the functions operating on the hidden debug registers into it's own file, port_hidden.c. The functions prefix is renamed from mv88e6390_hidden_ to mv88e6xxx_port_hidden_, to be consistent with the rest of this driver. The macros are prefixed with MV88E6XXX_ prefix, and are changed not to use the BIT() macro nor bit shifts, since the rest of the port.h file does not use it. We also add the support for setting the Block Address field when operating hidden registers. Marvell's mdio examples for SERDES settings on Topaz use Block Address 0x7 when reading/writing hidden registers, and although the specification says that block must be set to 0xf, those settings are reachable only with Block Address 0x7. Signed-off-by:
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Marek Behún authored
The mv88e6390_serdes_irq_link_sgmii IRQ handler reads the SERDES PHY status register to determine speed, among other things. If cmode of the port is set to 2500base-x, though, the PHY still reports 1000 Mbps (the PHY register itself does not differentiate between 1000 Mbps and 2500 Mbps - it thinks it is running at 1000 Mbps, although clock is 2.5x faster). Look at the cmode and set SPEED_2500 if cmode is set to 2500base-x. Also tell mv88e6xxx_port_setup_mac the PHY interface mode corresponding to current cmode in terms of phy_interface_t. Signed-off-by:
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David S. Miller authored
Xin Long says: ==================== sctp: add SCTP_ECN_SUPPORTED sockopt This patchset is to make ecn flag per netns and endpoint and then add SCTP_ECN_SUPPORTED sockopt, as does for other feature flags. ==================== Acked-by:
Neil Horman <nhorman@tuxdriver.com> Signed-off-by:
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Xin Long authored
SCTP_ECN_SUPPORTED sockopt will be added to allow users to change ep ecn flag, and it's similar with other feature flags. Signed-off-by:
Xin Long <lucien.xin@gmail.com> Signed-off-by:
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Xin Long authored
sysctl net.sctp.ecn_enable is added in this patch. It will allow users to change the default sctp ecn flag, net.sctp.ecn_enable. This feature was also required on this thread: http://lkml.iu.edu/hypermail/linux/kernel/0812.1/01858.htmlSigned-off-by:
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Xin Long authored
This patch is to add ecn flag for both netns_sctp and sctp_endpoint, net->sctp.ecn_enable is set 1 by default, and ep->ecn_enable will be initialized with net->sctp.ecn_enable. asoc->peer.ecn_capable will be set during negotiation only when ep->ecn_enable is set on both sides. Signed-off-by:
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Mao Wenan authored
Fixes gcc '-Wunused-but-set-variable' warning: drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function mtk_handle_irq: drivers/net/ethernet/mediatek/mtk_eth_soc.c:1951:6: warning: variable status set but not used [-Wunused-but-set-variable] Fixes: 296c9120 ("net: ethernet: mediatek: Add MT7628/88 SoC support") Signed-off-by:
Mao Wenan <maowenan@huawei.com> Reviewed-by:
Stefan Roese <sr@denx.de> Signed-off-by:
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David S. Miller authored
Vladimir Oltean says: ==================== Simplify DSA handling of VLAN subinterface offload Depends on Vivien Didelot's patchset: https://patchwork.ozlabs.org/project/netdev/list/?series=127197&state=* This patchset removes a few strange-looking guards for -EOPNOTSUPP in dsa_slave_vlan_rx_add_vid and dsa_slave_vlan_rx_kill_vid, making that code path no longer possible. It also disables the code path for the sja1105 driver, which does support editing the VLAN table, but not hardware-accelerated VLAN sub-interfaces, therefore the check in the DSA core would be wrong. There was no better DSA callback to do this than .port_enable, i.e. at ndo_open time. ==================== Signed-off-by:
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Vladimir Oltean authored
The switch barely supports traffic I/O, and it does that by repurposing VLANs when there is no bridge that is taking control of them. Letting DSA declare this netdev feature as supported (see dsa_slave_create) would mean that VLAN sub-interfaces created on sja1105 switch ports will be hardware offloaded. That means that net/8021q/vlan_core.c would install the VLAN into the filter tables of the switch, potentially interfering with the tag_8021q VLANs. We need to prevent that from happening and not let the 8021q core offload VLANs to the switch hardware tables. In vlan_filtering=0 modes of operation, the switch ports can pass through VLAN-tagged frames with no problem. Suggested-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
Vladimir Oltean <olteanv@gmail.com> Signed-off-by:
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Vladimir Oltean authored
When adding a VLAN sub-interface on a DSA slave port, the 8021q core checks NETIF_F_HW_VLAN_CTAG_FILTER and, if the netdev is capable of filtering, calls .ndo_vlan_rx_add_vid or .ndo_vlan_rx_kill_vid to configure the VLAN offloading. DSA sets this up counter-intuitively: it always advertises this netdev feature, but the underlying driver may not actually support VLAN table manipulation. In that case, the DSA core is forced to ignore the error, because not being able to offload the VLAN is still fine - and should result in the creation of a non-accelerated VLAN sub-interface. Change this so that the netdev feature is only advertised for switch drivers that support VLAN manipulation, instead of checking for -EOPNOTSUPP at runtime. Suggested-by:
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David S. Miller authored
René van Dorst says: ==================== net: ethernet: mediatek: convert to PHYLINK These patches converts mediatek driver to PHYLINK API. v3->v4: * Phylink improvements and clean-ups after review v2->v3: * Phylink improvements and clean-ups after review v1->v2: * Rebase for mt76x8 changes * Phylink improvements and clean-ups after review * SGMII port doesn't support 2.5Gbit in SGMII mode only in BASE-X mode. Refactor the code. ==================== Signed-off-by: -
René van Dorst authored
This patch the removes the recently added mediatek,physpeed property. Use the fixed-link property speed = <2500> to set the phy in 2.5Gbit. See mt7622-bananapi-bpi-r64.dts for a working example. Signed-off-by:
René van Dorst <opensource@vdorst.com> Signed-off-by:
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René van Dorst authored
* Re-add SGMII support but now with PHYLINK API support So the SGMII changes are more clear * Move SGMII block setup from mtk_gmac_sgmii_path_setup() to mtk_mac_config() * Merge mtk_setup_hw_path() into mtk_mac_config() * Remove mediatek,physpeed property, fixed-link supports now any speed so speed = <2500>; is now valid with PHYLINK * Demagic SGMII register values * Use phylink state to setup fixed-link mode Signed-off-by:
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René van Dorst authored
This convert the basics to PHYLINK API. SGMII support is not in this patch. Signed-off-by:
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David S. Miller authored
Vivien Didelot says: ==================== net: dsa: explicit programmation of VLAN on CPU ports When a VLAN is programmed on a user port, every switch of the fabric also program the CPU ports and the DSA links as part of the VLAN. To do that, DSA makes use of bitmaps to prepare all members of a VLAN. While this is expected for DSA links which are used as conduit between interconnected switches, only the dedicated CPU port of the slave must be programmed, not all CPU ports of the fabric. This may also cause problems in other corners of DSA such as the tag_8021q.c driver, which needs to program its ports manually, CPU port included. We need the dsa_port_vlan_{add,del} functions and its dsa_port_vid_{add,del} variants to simply trigger the VLAN programmation without any logic in them, but they may currently skip the operation based on the bridge device state. This patchset gets rid of the bitmap operations, and moves the bridge device check as well as the explicit programmation of CPU ports where they belong, in the slave code. While at it, clear the VLAN flags before programming a CPU port, as it doesn't make sense to forward the PVID flag for example for such ports. Changes in v2: only clear the PVID flag. ==================== Tested-by: -
Vivien Didelot authored
When the bridge offloads a VLAN on a slave port, we also need to program its dedicated CPU port as a member of the VLAN. Drivers may handle the CPU port's membership as they want. For example, Marvell as a special "Unmodified" mode to pass frames as is through such ports. Even though DSA expects the drivers to handle the CPU port membership, it does not make sense to program user VLANs as PVID on the CPU port. This patch clears this flag before programming the CPU port. Signed-off-by:
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Vivien Didelot authored
DSA currently programs a VLAN on the CPU port implicitly after the related notifier is received by a switch. While we still need to do this transparent programmation of the DSA links in the fabric, programming the CPU port this way may cause problems in some corners such as the tag_8021q driver. Because the dedicated CPU port is specific to a slave, make their programmation explicit a few layers up, in the slave code. Note that technically, DSA links have a dedicated CPU port as well, but since they are only used as conduit between interconnected switches of a fabric, programming them transparently this way is what we want. Signed-off-by:
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Vivien Didelot authored
The bridge VLANs are not offloaded by dsa_port_vlan_* if the port is not bridged or if its bridge is not VLAN aware. This is a good thing but other corners of DSA, such as the tag_8021q driver, may need to program VLANs regardless the bridge state. And also because bridge_dev is specific to user ports anyway, move these checks were it belongs, one layer up in the slave code. Signed-off-by:
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