- Drop endpoint redundant masking of global IRQ events (Manivannan
  Sadhasivam)

- Clarify unknown global IRQ message and only log it once to avoid a flood
  (Manivannan Sadhasivam)

- Add Manivannan Sadhasivam as maintainer of qcom endpoint driver
  (Manivannan Sadhasivam)

- Add 'linux,pci-domain' property to endpoint DT binding (Manivannan
  Sadhasivam)

- Assign PCI domain number for endpoint controllers (Manivannan Sadhasivam)

- Add 'qcom_pcie_ep' and the PCI domain number to IRQ names for endpoint
  controller (Manivannan Sadhasivam)

- Add global SPI interrupt for PCIe link events to DT binding (Manivannan
  Sadhasivam)

- Add global RC interrupt handler to handle 'Link up' events and
  automatically enumerate hot-added devices (Manivannan Sadhasivam)

- Avoid mirroring of DBI and iATU register space so it doesn't overlap BAR
  MMIO space (Prudhvi Yarlagadda)

- Enable controller resources like PHY only after PERST# is deasserted to
  partially avoid the problem that the endpoint SoC crashes when accessing
  things when Refclk is absent (Manivannan Sadhasivam)

- Rename dw_pcie.link_gen to max_link_speed to avoid ambiguity (Manivannan
  Sadhasivam)

- Cache maximum link speed value in dw_pcie.max_link_speed for use by
  vendor drivers (Manivannan Sadhasivam)

- Add 16.0 GT/s equalization and RX lane margining settings (Shashank Babu
  Chinta Venkata)

- Pass domain number to pci_bus_release_domain_nr() explicitly to avoid a
  NULL pointer dereference (Manivannan Sadhasivam)

* pci/controller/qcom:
  PCI: Pass domain number to pci_bus_release_domain_nr() explicitly
  PCI: qcom: Add RX lane margining settings for 16.0 GT/s
  PCI: qcom: Add equalization settings for 16.0 GT/s
  PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
  PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
  PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
  PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region
  PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt
  dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt
  PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names
  PCI: endpoint: Assign PCI domain number for endpoint controllers
  dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property
  dt-bindings: PCI: pci-ep: Update Maintainers
  PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event
  PCI: qcom-ep: Drop the redundant masking of global IRQ events

- Add per-SoC struct mtk_gen3_pcie_pdata to support multiple SoC types
  (Lorenzo Bianconi)

- Use reset_bulk APIs to manage PHY reset lines (Lorenzo Bianconi)

- Add DT and driver support for Airoha EN7581 PCIe controller (Lorenzo
  Bianconi)

* pci/controller/mediatek-gen3:
  PCI: mediatek-gen3: Add Airoha EN7581 support
  PCI: mediatek-gen3: Rely on reset_bulk APIs for PHY reset lines
  PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data structure
  dt-bindings: PCI: mediatek-gen3: Add support for Airoha EN7581

- Drop excess mtk_pcie.mem kerneldoc description (Bjorn Helgaas)

* pci/controller/mediatek:
  PCI: mediatek: Drop excess mtk_pcie.mem kerneldoc description

- Increase max PCI hosts to 8 for Loongson-3C6000 and newer chipsets
  (Huacai Chen)

* pci/controller/loongson:
  PCI/ACPI: Increase Loongson max PCI hosts to 8

- Fix potential buffer overflow in kirin_pcie_parse_port() (Alexandra
  Diupina)

* pci/controller/kirin:
  PCI: kirin: Fix buffer overflow in kirin_pcie_parse_port()

- Fix NULL pointer checking when applying MRRS limitation quirk for AM65x
  SR 1.0 Errata #i2037 (Dan Carpenter)

* pci/controller/keystone:
  PCI: keystone: Fix if-statement expression in ks_pcie_quirk()

- Add DT "ti,syscon-acspcie-proxy-ctrl" and driver support to enable the
  ACSPCIE module to drive Refclk for the Endpoint (Siddharth Vadapalli)

- Extract the cadence link setup from cdns_pcie_host_setup() so link setup
  can be done separately during resume (Thomas Richard)

- Use dev_err_probe() to simplify j721e probe (Thomas Richard)

- Add T_PERST_CLK_US definition for the mandatory delay between Refclk
  becoming stable and PERST# being deasserted (Thomas Richard)

- Add j721e suspend and resume support (Théo Lebrun)

* pci/controller/j721e:
  PCI: j721e: Add suspend and resume support
  PCI: j721e: Use T_PERST_CLK_US macro
  PCI: Add T_PERST_CLK_US macro
  PCI: j721e: Add reset GPIO to struct j721e_pcie
  PCI: j721e: Use dev_err_probe() in the probe() function
  PCI: cadence: Set cdns_pcie_host_init() global
  PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup()
  PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" exists
  dt-bindings: PCI: ti,j721e-pci-host: Add ACSPCIE proxy control property

- Fix a code restructuring error that caused i.MX8MM and i.MX8MP Endpoints
  to fail to establish link (Richard Zhu)

- Fix i.MX8MP Endpoint occasional failure to trigger MSI by enforcing
  outbound alignment requirement (Richard Zhu)

- Call phy_power_off() in the .probe() error path (Frank Li)

- Rename internal names from imx6_* to imx_* since i.MX7/8/9 are also
  supported (Frank Li)

- Manage Refclk by using SoC-specific callbacks instead of switch
  statements (Frank Li)

- Manage core reset by using SoC-specific callbacks instead of switch
  statements (Frank Li)

- Expand comments for erratum ERR010728 workaround (Frank Li)

- Use generic PHY APIs to configure mode, speed, and submode, which is
  harmless for devices that implement their own internal PHY management and
  don't set the generic imx_pcie->phy (Frank Li)

- Add i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) DT binding and driver Root
  Complex support (Richard Zhu)

* pci/controller/imx6:
  PCI: imx6: Add i.MX8Q PCIe Root Complex (RC) support
  PCI: imx6: Call common PHY API to set mode, speed, and submode
  dt-bindings: PCI: imx6q-pcie: Add i.MX8Q PCIe compatible string
  PCI: imx6: Consolidate redundant if-checks
  PCI: imx6: Improve comment for workaround ERR010728
  PCI: imx6: Simplify switch-case logic by involve core_reset callback
  PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
  PCI: imx6: Rename imx6_* with imx_*
  PCI: imx6: Fix missing call to phy_power_off() in error handling
  PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI
  PCI: imx6: Fix establish link failure in EP mode for i.MX8MM and i.MX8MP

- Request IRQF_ONESHOT for 'dra7xx-pcie-main' IRQ since the primary handler
  is NULL (Siddharth Vadapalli)

- Handle IRQ request errors during root port and endpoint probe (Siddharth
  Vadapalli)

* pci/controller/dra7xx:
  PCI: dra7xx: Fix error handling when IRQ request fails in probe
  PCI: dra7xx: Fix threaded IRQ request for "dra7xx-pcie-main" IRQ

- Drop excess cdns_pcie_rc.dev kerneldoc description (Bjorn Helgaas)

* pci/controller/cadence:
  PCI: cadence: Drop excess cdns_pcie_rc.dev kerneldoc description

- Change DT binding maintainer to Jim Quinlan (Jim Quinlan)

- Add DT binding maxItems for reset controllers (Jim Quinlan)

- Refactor .probe() error handling (Jim Quinlan)

- Use the 'bridge' reset method if described in the DT (Jim Quinlan)

- Use the 'swinit' reset method if described in the DT (Jim Quinlan)

- Add SoC-specific HARD_DEBUG, INTR2_CPU_BASE register offsets (Jim
  Quinlan)

- Drop unused RGR1_SW_INIT_1_INIT_MASK, RGR1_SW_INIT_1_INIT_SHIFT offsets
  (Jim Quinlan)

- Add 'has_phy' so the existence of a 'rescal' reset controller doesn't
  imply software control of it (Jim Quinlan)

- Add support for many inbound DMA windows (Jim Quinlan)

- Check return values of all reset_control_*() calls (Jim Quinlan)

- Rename SoC 'type' to 'soc_base' express the fact that SoCs come in
  families of multiple similar devices (Jim Quinlan)

- Add Broadcom 7712 DT description and driver support (Jim Quinlan)

- Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings for
  maintainability (Bjorn Helgaas)

* pci/controller/brcmstb:
  PCI: brcmstb: Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings
  PCI: brcmstb: Enable 7712 SoCs
  PCI: brcmstb: Change field name from 'type' to 'soc_base'
  PCI: brcmstb: Check return value of all reset_control_* calls
  PCI: brcmstb: Refactor for chips with many regular inbound windows
  PCI: brcmstb: Don't conflate the reset rescal with PHY ctrl
  PCI: brcmstb: Remove two unused constants from driver
  PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific
  PCI: brcmstb: Use swinit reset if available
  PCI: brcmstb: Use bridge reset if available
  PCI: brcmstb: Use common error handling code in brcm_pcie_probe()
  dt-bindings: PCI: brcm,stb-pcie: Add 7712 SoC description
  dt-bindings: PCI: brcm,stb-pcie: Use maxItems for reset controllers
  dt-bindings: PCI: brcm,stb-pcie: Change brcmstb maintainer and cleanup

- Replace TLP_REQ_ID() with macro PCI_DEVID(), which does the same thing
  and is what other drivers use (Jinjie Ruan)

* pci/controller/altera:
  PCI: altera: Replace TLP_REQ_ID() with macro PCI_DEVID()

- Add MSI_FLAG_NO_AFFINITY flag for devices that mux MSIs onto a single IRQ
  line and cannot set the affinity of each MSI to a specific CPU core
  (Marek Vasut)

- Use MSI_FLAG_NO_AFFINITY and remove unnecessary .irq_set_affinity()
  implementations in aardvark, altera, brcmstb, dwc, mediatek-gen3,
  mediatek, mobiveil, plda, rcar, tegra, vmd, xilinx-nwl, xilinx-xdma, and
  xilinx drivers to avoid "IRQ: set affinity failed" warnings (Marek Vasut)

* pci/controller/affinity:
  PCI: xilinx: Silence 'set affinity failed' warning
  PCI: xilinx-xdma: Silence 'set affinity failed' warning
  PCI: xilinx-nwl: Silence 'set affinity failed' warning
  PCI: vmd: Silence 'set affinity failed' warning
  PCI: tegra: Silence 'set affinity failed' warning
  PCI: rcar-host: Silence 'set affinity failed' warning
  PCI: plda: Silence 'set affinity failed' warning
  PCI: mobiveil: Silence 'set affinity failed' warning
  PCI: mediatek: Silence 'set affinity failed' warning
  PCI: mediatek-gen3: Silence 'set affinity failed' warning
  PCI: dwc: Silence 'set affinity failed' warning
  PCI: brcmstb: Silence 'set affinity failed' warning
  PCI: altera-msi: Silence 'set affinity failed' warning
  PCI: aardvark: Silence 'set affinity failed' warning
  genirq/msi: Silence 'set affinity failed' warning

- Fix enum pci_epc_bar_type kerneldoc (Bjorn Helgaas)

* pci/controller/endpoint:
  PCI: endpoint: Fix enum pci_epc_bar_type kerneldoc

- Drop minItems and maxItems from ranges in PCI generic host binding since
  host bridges may have several MMIO and I/O port apertures (Frank Li)

- Add kirin, rcar-gen2, uniphier DT binding top-level constraints for
  clocks (Krzysztof Kozlowski)

- Replace layerscape-pcie DT binding compatible fsl,lx2160a-pcie with
  fsl,lx2160ar2-pcie (Frank Li)

- Add layerscape-pcie DT binding deprecated 'num-viewport' property to
  address a DT checker warning (Frank Li)

- Change layerscape-pcie DT binding 'fsl,pcie-scfg' to phandle-array (Frank
  Li)

- Update qcom,pcie-sc7280 DT binding with eight interrupts (Rayyan Ansari)

- Convert altera DT bindings from text to YAML (Matthew Gerlach)

- Add imx6q-pcie 'dbi2' and 'atu' reg-names for i.MX8M Endpoints (Richard
  Zhu)

- Add back qcom 'vddpe-3v3-supply', which was incorrectly removed earlier
  (Johan Hovold)

* pci/dt-bindings:
  dt-bindings: PCI: qcom: Allow 'vddpe-3v3-supply' again
  dt-bindings: PCI: imx6q-pcie: Add reg-name "dbi2" and "atu" for i.MX8M PCIe Endpoint
  dt-bindings: PCI: altera: msi: Convert to YAML
  dt-bindings: PCI: altera: Convert to YAML
  dt-bindings: PCI: qcom,pcie-sc7280: Update bindings adding eight interrupts
  dt-bindings: PCI: layerscape-pci: Change property 'fsl,pcie-scfg' type
  dt-bindings: PCI: layerscape-pci: Add deprecated property 'num-viewport'
  dt-bindings: PCI: layerscape-pci: Replace fsl,lx2160a-pcie with fsl,lx2160ar2-pcie
  dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints
  dt-bindings: PCI: renesas,pci-rcar-gen2: Add top-level constraints
  dt-bindings: PCI: hisilicon,kirin-pcie: Add top-level constraints
  dt-bindings: PCI: host-generic-pci: Drop minItems and maxItems of ranges

- Add ARCH_PCI_DEV_GROUPS so s390 can add its own attribute_groups without
  having to stomp on the core's pdev->dev.groups (Lukas Wunner)

* pci/sysfs:
  s390/pci: Stop usurping pdev->dev.groups

- Wait for each level of downstream bus, not just the first, to become
  accessible before restoring devices on that bus (Ilpo Järvinen)

* pci/reset:
  PCI: Wait for Link before restoring Downstream Buses

- Add pwrctl support for ATH11K inside the WCN6855 package (Konrad Dybcio)

* pci/pwrctl:
  PCI/pwrctl: Add WCN6855 support

- Initialize leds class earlier (with an unfortunate Makefile ordering
  change) so the PCI NPEM driver can use it (Mariusz Tkaczyk)

- Add Native PCIe Enclosure Management (NPEM) support for sysfs control of
  NVMe RAID storage indicators (ok/fail/locate/rebuild/etc) (Mariusz
  Tkaczyk)

- Add support for the ACPI _DSM PCIe SSD status LED management, which is
  functionally similar to NPEM but mediated by platform firmware (Mariusz
  Tkaczyk)

* pci/npem:
  PCI/NPEM: Add _DSM PCIe SSD status LED management
  PCI/NPEM: Add Native PCIe Enclosure Management support
  leds: Init leds class earlier

- Add function 0 DMA alias quirk for Glenfly Arise audio function, which
  uses the function 0 Requester ID (WangYuli)

* pci/iommu:
  PCI: Add function 0 DMA alias quirk for Glenfly Arise chip

- Remove unnecessary hpc_ops struct from shpchp (ngn)

- Check for PCI_POSSIBLE_ERROR(), not 0xffffffff, in cpqphp (weiyufeng)

* pci/hotplug:
  PCI: cpqphp: Use PCI_POSSIBLE_ERROR() to check config reads
  PCI: shpchp: Remove hpc_ops

- Clear LBMS bit after a manual link retrain so we don't try to retrain a
  link when there's no downstream device anymore (Maciej W. Rozycki)

- Revert to the original link speed after retraining fails instead of
  leaving it restricted to 2.5GT/s, so a future device has a chance to use
  higher speeds (Maciej W. Rozycki)

- Correct interpretation of pcie_retrain_link() return status and update it
  to return 0/errno instead of true/false (Maciej W.  Rozycki)

* pci/enumeration:
  PCI: Use an error code with PCIe failed link retraining
  PCI: Correct error reporting with PCIe failed link retraining
  PCI: Revert to the original speed after PCIe failed link retraining
  PCI: Clear the LBMS bit after a link retrain

- Export pcim_request_region(), a managed counterpart of
  pci_request_region(), for use by drivers (Philipp Stanner)

- Request the PCI BAR used by xboxvideo (Philipp Stanner)

- Export pcim_iomap_region() and deprecate pcim_iomap_regions() (Philipp
  Stanner)

- Request and map drm/ast BARs with pcim_iomap_region() (Philipp Stanner)

* pci/devres:
  drm/ast: Request PCI BAR with devres
  PCI: Deprecate pcim_iomap_regions() in favor of pcim_iomap_region()
  drm/vboxvideo: Add PCI region request
  PCI: Make pcim_request_region() a public function

- Wait for device readiness after reset by polling Vendor ID and looking
  for Configuration RRS instead of polling the Command register and looking
  for non-error completions (Bjorn Helgaas)

- Fix an aardvark issue with emulating Configuration RRS for two-byte reads
  of Vendor ID; previously it only worked for four-byte reads (Bjorn
  Helgaas)

- Rename CRS Completion Status to RRS to match spec usage (Bjorn Helgaas)

* pci/crs:
  PCI: Rename CRS Completion Status to RRS
  PCI: aardvark: Correct Configuration RRS checking
  PCI: Wait for device readiness with Configuration RRS

- Use PCI_DEVID() macro in aer_inject() instead of open-coding it (Jinjie
  Ruan)

* pci/aer:
  PCI/AER: Use PCI_DEVID() macro in aer_inject()

Commit 756485bf ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to
dedicated schema") incorrectly removed 'vddpe-3v3-supply' from the
bindings, which results in DT checker warnings like:

  arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dtb: pcie@600000: Unevaluated properties are not allowed ('vddpe-3v3-supply' was unexpected)
  from schema $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#

Note that this property has been part of the Qualcomm PCIe bindings since
2018 and would need to be deprecated rather than simply removed if there is
a desire to replace it with 'vpcie3v3' which is used for some non-Qualcomm
controllers.

Link: https://lore.kernel.org/lkml/Zp_LPixNnh-2Fy5N@hovoldconsulting.com/
Fixes: 756485bf ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema")
Link: https://lore.kernel.org/r/20240723151328.684-1-johan+linaro@kernel.orgSigned-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

The pci_bus_release_domain_nr() API is supposed to free the domain
number allocated by pci_bus_find_domain_nr(). Most of the callers of
pci_bus_find_domain_nr(), store the domain number in pci_bus::domain_nr.

As such, the pci_bus_release_domain_nr() implicitly frees the domain
number by dereferencing 'struct pci_bus'. However, one of the callers
of this API, the PCI endpoint subsystem, doesn't have 'struct pci_bus',
so it only passes NULL. Due to this, the API will end up dereferencing
the NULL pointer.

To fix this issue, pass the domain number to this API explicitly. Since
'struct pci_bus' is not used for anything else other than extracting the
domain number, it makes sense to pass the domain number directly.

Fixes: 0328947c ("PCI: endpoint: Assign PCI domain number for endpoint controllers")
Closes: https://lore.kernel.org/linux-pci/c0c40ddb-bf64-4b22-9dd1-8dbb18aa2813@stanley.mountain
Link: https://lore.kernel.org/linux-pci/20240912053025.25314-1-manivannan.sadhasivam@linaro.orgReported-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>

Commit d4c7d1a0 ("PCI: dwc: dra7xx: Push request_irq()
call to the bottom of probe") moved the IRQ request for
"dra7xx-pcie-main" towards the end of dra7xx_pcie_probe().

However, the error handling does not take into account the
initialization performed by either dra7xx_add_pcie_port() or
dra7xx_add_pcie_ep(), depending on the mode of operation.

Fix the error handling to address this.

Fixes: d4c7d1a0 ("PCI: dwc: dra7xx: Push request_irq() call to the bottom of probe")
Link: https://lore.kernel.org/linux-pci/20240827122422.985547-3-s-vadapalli@ti.comTested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org

Commit da87d35a ("PCI: dra7xx: Use threaded IRQ handler for
"dra7xx-pcie-main" IRQ") switched from devm_request_irq() to
devm_request_threaded_irq() for the "dra7xx-pcie-main" interrupt.

Since the primary handler was set to NULL, the "IRQF_ONESHOT" flag
should have also been set. Fix this.

Fixes: da87d35a ("PCI: dra7xx: Use threaded IRQ handler for "dra7xx-pcie-main" IRQ")
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/linux-pci/20240827122422.985547-2-s-vadapalli@ti.comReported-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org

Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate.

These settings improve link stability while operating at high date
rates and helps to improve signal quality.

Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-4-743f5c1fd027@linaro.orgTested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
[mani: dropped the code refactoring and minor changes]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

During high data transmission rates such as 16.0 GT/s, there is an
increased risk of signal loss due to poor channel quality and
interference. This can impact receiver's ability to capture signals
accurately.

Hence, as signal compensation is achieved through appropriate lane
equalization, apply lane equalization settings at both transmitter
and receiver which results in an increase in the PCIe signal strength.

While at it, modify the pcie-tegra194 driver to make use of the
common GEN3_EQ_CONTROL_OFF definitions in pcie-designware.h.

Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-3-743f5c1fd027@linaro.orgTested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
[mani: dropped the code refactoring and minor changes]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Currently, the dw_pcie::max_link_speed has a valid value only if the
controller driver restricts the maximum link speed in the driver or if
the platform does so in the devicetree using the 'max-link-speed'
property.

But having the maximum supported link speed of the platform would be
helpful for the vendor drivers to configure any link specific settings.

So in the case of non-valid value in dw_pcie::max_link_speed, just cache
the hardware default value from Link Capability register.

While at it, remove the 'max_link_speed' argument to the
dw_pcie_link_set_max_speed() function since the value can be
retrieved within the function.

Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-2-743f5c1fd027@linaro.orgTested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>

The 'link_gen' field is now holding the maximum supported link speed set
either by the controller driver or by DT through 'max-link-speed'
property.

However, the name 'link_gen' sounds like the negotiated link speed of
the PCIe link.

So rename it to 'max_link_speed' to make it clear that it holds the
maximum supported link speed of the controller.

Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-1-743f5c1fd027@linaro.orgTested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>

qcom_pcie_enable_resources() is called by qcom_pcie_ep_probe() and it
enables the controller resources like clocks, regulator, PHY. On one of the
new unreleased Qcom SoC, PHY enablement depends on the active refclk. And
on all of the supported Qcom endpoint SoCs, refclk comes from the host
(RC). So calling qcom_pcie_enable_resources() without refclk causes the
NoC (Network On Chip) error in the endpoint SoC and in turn results in a
whole SoC crash and rebooting into EDL (Emergency Download) mode which is
an unrecoverable state.

But qcom_pcie_enable_resources() is already called by
qcom_pcie_perst_deassert() when PERST# is deasserted, and refclk is
available at that time.

Hence, remove the unnecessary call to qcom_pcie_enable_resources() from
qcom_pcie_ep_probe() to prevent the above mentioned crash.

It should be noted that this commit prevents the crash only under normal
working condition (booting endpoint before host), but the crash may also
occur if PERST# assert happens at the wrong time. For avoiding the crash
completely, it is recommended to use SRIS mode which allows the endpoint
SoC to generate its own refclk. The driver is not supporting SRIS mode
currently, but will be added in the future.

Fixes: 869bc525 ("PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host")
Link: https://lore.kernel.org/linux-pci/20240830082319.51387-1-manivannan.sadhasivam@linaro.orgTested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>

Add reg-name: "dbi2", "atu" for i.MX8M PCIe Endpoint.

For i.MX8M PCIe EP, the dbi2 and atu addresses are pre-defined in the
driver. This method is not good.

In commit b7d67c61 ("PCI: imx6: Add iMX95 Endpoint (EP) support"),
Frank suggests to fetch the dbi2 and atu from DT directly. This commit is
preparation to do that for i.MX8M PCIe EP.

These changes wouldn't break driver function. When "dbi2" and "atu"
properties are present, i.MX PCIe driver would fetch the according base
addresses from DT directly. If only two reg properties are provided, i.MX
PCIe driver would fall back to the old method.

Link: https://lore.kernel.org/linux-pci/1723534943-28499-2-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Convert the devicetree bindings for the Altera PCIe MSI controller
from text to YAML.

Link: https://lore.kernel.org/linux-pci/20240717181756.2177553-1-matthew.gerlach@linux.intel.comSigned-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
[kwilczynski: remove unused msi0 label]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe Root Complex
(RC) support. While the controller resembles that of i.MX8MP, the PHY
differs significantly. Also, there's a distinction between PCI bus
addresses and CPU addresses.

Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver
need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus
address conversion according to "ranges" property.

Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-11-b68ee5ef2b4d@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: check resource_list_first_type() for NULL]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

PCIe r6.0 changed the abbreviation for "Configuration Request Retry Status"
Completion Status from "CRS" to "RRS" and uses the terminology of
"Configuration RRS Software Visibility" instead of "CRS Software
Visibility".

Align the Linux usage with the r6.0 spec language.  No functional change
intended.

It's confusing to make this change, but I think "RRS" *is* a better
abbreviation because it was easy to interpret "CRS" as "Completion Retry
Status", which really didn't make any sense.

Link: https://lore.kernel.org/r/20240827234848.4429-4-helgaas@kernel.orgSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>

Per PCIe r6.0, sec 2.3.2, when a Root Complex handles a Completion with
Request Retry Status for a Configuration Read Request that includes both
bytes of the Vendor ID field, it must complete the Request to the host by
returning 0001h for the Vendor ID and all 1's for any additional bytes.

Previously we only returned the 0001h Vendor ID value if we got an RRS
completion for reads of exactly 4 bytes.  A read of 2 bytes would not
qualify, although the spec says it should.

Check for reads of 2 or more bytes including the Vendor ID.

I don't think this will fix any observable problems because RRS only
applies to the first config reads after reset, and those are all currently
dword (4-byte) reads.

Link: https://lore.kernel.org/r/20240827234848.4429-3-helgaas@kernel.orgSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>

After a device reset, delays are required before the device can
successfully complete config accesses.  PCIe r6.0, sec 6.6, specifies some
delays required before software can perform config accesses.  Devices that
require more time after those delays may respond to config accesses with
Configuration Request Retry Status (RRS) completions.

Callers of pci_dev_wait() are responsible for delays until the device can
respond to config accesses.  pci_dev_wait() waits any additional time until
the device can successfully complete config accesses.

Reading config space of devices that are not present or not ready typically
returns ~0 (PCI_ERROR_RESPONSE).  Previously we polled the Command register
until we got a value other than ~0.  This is sometimes a problem because
Root Complex handling of RRS completions may include several retries and
implementation-specific behavior that is invisible to software (see sec
2.3.2), so the exponential backoff in pci_dev_wait() may not work as
intended.

Linux enables Configuration RRS Software Visibility on all Root Ports that
support it.  If it is enabled, read the Vendor ID instead of the Command
register.  RRS completions cause immediate return of the 0x0001 reserved
Vendor ID value, so the pci_dev_wait() backoff works correctly.

When a read of Vendor ID eventually completes successfully by returning a
non-0x0001 value (the Vendor ID or 0xffff for VFs), the device should be
initialized and ready to respond to config requests.

For conventional PCI devices or devices below Root Ports that don't support
Configuration RRS Software Visibility, poll the Command register as before.

This was developed independently, but is very similar to Stanislav
Spassov's previous work at
https://lore.kernel.org/linux-pci/20200223122057.6504-1-stanspas@amazon.com

Link: https://lore.kernel.org/r/20240827234848.4429-2-helgaas@kernel.orgSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Duc Dang <ducdang@google.com>