- 16 Feb, 2012 2 commits
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Dave Airlie authored
The current enabling of bus mastering in the drm midlayer allows a large race condition under kexec. When a kexec'ed kernel re-enables bus mastering for the GPU, previously setup dma blocks may cause writes to random pieces of memory. On radeon the writeback mechanism can cause these sorts of issues. This patch doesn't fix the problem, but it moves the bus master enable under the individual drivers control so they can move enabling it until later in their load cycle and close the race. Fix for radeon kms driver will be in a follow-up patch. Signed-off-by:Dave Airlie <airlied@redhat.com>
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Dan Carpenter authored
We store stuff in texdw[7] so this array needs to have 8 elements. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Jerome Glisse <jglisse@redhat.com> Signed-off-by:
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- 14 Feb, 2012 1 commit
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Dave Airlie authored
Merge tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next * tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm-intel: (29 commits) drm/i915: Handle unmappable buffers during error state capture drm/i915: rewrite shmem_pread_slow to use copy_to_user drm/i915: rewrite shmem_pwrite_slow to use copy_from_user drm/i915: fall through pwrite_gtt_slow to the shmem slow path drm/i915: add debugfs file for swizzling information drm/i915: fix swizzle detection for gen3 drm/i915: Remove the upper limit on the bo size for mapping into the CPU domain drm/i915: add per-ring fault reg to error_state drm/i915: reject GTT domain in relocations drm/i915: remove the i915_batchbuffer_info debugfs file drm/i915: capture error_state also for stuck rings drm/i915: refactor debugfs create functions drm/i915: refactor debugfs open function drm/i915: don't trash the gtt when running out of fences drm/i915: Separate fence pin counting from normal bind pin counting drm/i915/ringbuffer: kill snb blt workaround drm/i915: collect more per ring error state drm/i915: refactor ring error state capture to use arrays drm/i915: switch ring->id to be a real id drm/i915: set AUD_CONFIG N_value_index for DisplayPort ...
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- 13 Feb, 2012 14 commits
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Jerome Glisse authored
evergreen and northern island gpu needs more informations for 2D tiling than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace to provide those. The v8 cs checking change to track color view on r6xx/r7xx doesn't affect old userspace as old userspace always emited 0 for this register. v2 fix r6xx/r7xx 2D tiling computation v3 fix r6xx/r7xx height align for untiled surface & add support for tile split on evergreen and newer v4 improve tiling debugging output v5 fix tile split code for evergreen and newer v6 set proper tile split for crtc register v7 fix tile split limit value v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs checking, update safe reg for r600, evergreen and cayman. Evergreen checking need some work around for stencil alignment issues v9 fix tile split value range, fix compressed texture handling and mipmap calculation, allow evergreen check to be silencious in front of current broken userspace (depth/stencil alignment issue) v10 fix eg 3d texture and compressed texture, fix r600 depth array, fix r600 color view computation, add support for evergreen stencil split v11 more verbose debugging in some case Signed-off-by: -
Marek Olšák authored
v2: agd5f: add strmout CS checking, copy_dw register checking v3: agd5f: don't use cs_check_reg() for copy_dw checking as it will incorrectly patch the command stream for certain regs. v4: agd5f: add warning if safe reg check fails for copy_dw v5: agd5f: add stricter checking for 6xx/7xx v6: agd5f: add range checking for copy_dw on eg+, add sx_surface_sync to safe reg list for 7xx. v7: agd5f: add stricter checking for eg+ Signed-off-by:
Marek Olšák <maraeo@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Axel Lin authored
The first parameter should be "number of elements" and the second parameter should be "element size". Signed-off-by:
Axel Lin <axel.lin@gmail.com> Acked-by:
Alan Cox <alan@linux.intel.com> Signed-off-by:
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Dave Airlie authored
* drm-vmware-next: drm/vmwgfx: Bump driver minor vmwgfx: Move function declaration to correct header drm/vmwgfx: Treat out-of-range initial width and height as host errors vmwgfx: Pick up the initial size from the width and height regs vmwgfx: Add page flip support vmwgfx: Pipe fence out of screen object dirty functions vmwgfx: Make it possible to get fence from execbuf vmwgfx: Clean up pending event references to struct drm_file objects on close vmwgfx: Rework fence event action
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Thomas Hellstrom authored
Bump driver minor to signal availability of the page-flip ioctl. Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by:
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Thomas Hellstrom authored
Signed-off-by:
Jakob Bornecrantz <jakob@vmware.com> Signed-off-by:
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Thomas Hellstrom authored
And assign the initial width and height to the minimum in that case. Strange values (-1) from these registers have been reported by users. Signed-off-by:
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Jakob Bornecrantz authored
Signed-off-by:
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Jakob Bornecrantz authored
Signed-off-by:
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Jakob Bornecrantz authored
Signed-off-by:
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Jakob Bornecrantz authored
Signed-off-by:
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Thomas Hellstrom authored
Pending events may have stale pointer references to struct drm_file objects after a file has been closed, but before the event is supposed to be attached to the drm file. Remove such events on file close. Tested with "modetest". Signed-off-by:
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Jakob Bornecrantz authored
Signed-off-by:
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Daniel Vetter authored
CEA actually specifies an interlaced mode with even vtotal and supplies a diagram showing how this is supposed to work. Note that interlaced modes with an even vtotal seem to be a fairly recent invention. All modelines lore I could dig up with googling says that vtotal for interlaced modes _needs_ to be odd. But the even modelines in CEA are not a spec-bug, there's a figure in CEA-861-E called "Figure 5 Special Interlaced Video Format Timing (Even Vtotal)" that explains how it's supposed to work. Furthermore intel Bspec explicitly mentions that both odd and even interlaced vtotal are supported (VTOTAL register in the south display engine of PCH split chips). Acked-by:
Adam Jackson <ajax@redhat.com> Signed-Off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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- 09 Feb, 2012 3 commits
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Sascha Hauer authored
The drm drivers set the fb_info->pixmap fields without setting fb_info->pixmap.addr. If this is not set the fb core will overwrite these all fb_info->pixmap fields anyway, so there is not much point in setting them in the first place. [airlied: dropped nvidiafb piece - not mine] Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
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Sascha Hauer authored
Creating a range property is a common pattern, so create a convenience function for this and use it where appropriate. Signed-off-by:
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Sascha Hauer authored
Creating an enum property is a common pattern, so create a convenience function for this and use it where appropriate. Signed-off-by:
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- 07 Feb, 2012 1 commit
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git://people.freedesktop.org/~danvet/drm-intelDave Airlie authored
* 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: add a LLC feature flag in device description drm/i915: kill i915_mem.c drm/i915: Use kcalloc instead of kzalloc to allocate array drm/i915/dp: Check for AUXCH error before checking for success drm/i915/dp: Use auxch precharge value of 5 everywhere drm/i915/dp: Tweak auxch clock divider for PCH drm/i915: Remove a comment about PCH from the non-PCH path drm/i915: Fix assert_pch_hdmi_disabled to mention HDMI (not DP) drm/i915: Implement plane-disabled assertion for PCH too drivers: i915: Fix BLC PWM register setup drm/i915: Check that plane/pipe is disabled before removing the fb drm/i915: fix typo in function name drm/i915: split out pll divider code drm/i915: split 9xx refclk & sdvo tv code out agp/intel: Add pci id for hostbridge from has/qemu drm/i915: there is no pipe CxSR on ironlake drm/i915: Only look for matching clocks for LVDS downclock drm/i915: Silence _DSM errors
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- 03 Feb, 2012 19 commits
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Sascha Hauer authored
info->fix.visual already is correctly set from drm_fb_helper_fill_fix. info->fix.line_length is also set from drm_fb_helper_fill_fix, so drm_fb_helper_set_par directly instead of a custom exynos_drm_fbdev_set_par. Signed-off-by:
Inki Dae <inki.dae@samsung.com> Signed-off-by:
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Sascha Hauer authored
list_for_each_entry_safe is for walking a list safe against removal of entries. Here, no entries are removed, so use list_for_each_entry. Signed-off-by:
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Sascha Hauer authored
Several comments above functions say that the caller must hold the mode_config lock, but the functions take the lock themselves. Fix the comments. Signed-off-by:
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Sascha Hauer authored
crtc_id is set but never used, so remove it from struct drm_fb_helper_crtc. Signed-off-by:
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Sascha Hauer authored
conn_limit is set but never used. Remove it from struct drm_fb_helper. Signed-off-by:
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Sascha Hauer authored
drm_fb_helper_on|off currently manually searches for encoders to turn on/off. Make this simpler by using the helper function. Signed-off-by:
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Sascha Hauer authored
drm_mode_crtc_set_gamma_size returns boolean true for success and false for failure. This is not very kernel conform, so change it to return 0 for success and a propert error code otherwise. Noone checks the return value, so no users have to be fixed. Signed-off-by:
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Sascha Hauer authored
drm_setup_crtcs allocated modes using drm_mode_duplicate. Free them in drm_fb_helper_crtc_free. Signed-off-by:
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Sascha Hauer authored
Modes are created using drm_mode_create which does a drm_mode_object_get, so use drm_mode_destroy in drm_mode_remove which does a drm_mode_object_put. Signed-off-by:
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Sascha Hauer authored
to add the missing drm_mode_object_put for that mode. Signed-off-by:
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Sascha Hauer authored
drm_mode_config_init initializes the idr with idr_init, so add the missing counterparts in drm_mode_config_cleanup. Signed-off-by:
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Alex Deucher authored
Not likely this will be implemented anytime soon, but for completeness... Signed-off-by:
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Alex Deucher authored
Previous patch only updates r3xx+. It's not likely anyone will use this on r1xx/r2xx, but add it for consistency. Signed-off-by:
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Eugeni Dodonov authored
This allows to avoid talking to a non-responding bus repeatedly until we finally timeout after 15 attempts. We can do this by catching the -ENXIO error, provided by i2c_algo_bit:bit_doAddress call. Within the bit_doAddress we already try 3 times to get the edid data, so if the routine tells us that bus is not responding, it is mostly pointless to keep re-trying those attempts over and over again until we reach final number of retries. This change should fix https://bugs.freedesktop.org/show_bug.cgi?id=41059 and improve overall edid detection timing by 10-30% in most cases, and by a much larger margin in case of phantom outputs (up to 30x in one worst case). Timing results for i915-powered machines for 'time xrandr' command: Machine 1: from 0.840s to 0.290s Machine 2: from 0.315s to 0.280s Machine 3: from +/- 4s to 0.184s Timing results for HD5770 with 'time xrandr' command: Machine 4: from 3.210s to 1.060s Reviewed-by:
Chris Wilson <chris@hchris-wilson.co.uk> Reviewed-by:
Keith Packard <keithp@keithp.com> Tested-by:
Sean Finney <seanius@seanius.net> Tested-by:
Soren Hansen <soren@linux2go.dk> Tested-by:
Hernando Torque <sirius@sonnenkinder.org> Tested-by:
Mike Lothian <mike@fireburn.co.uk> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41059Signed-off-by:
Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by:
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Alex Deucher authored
Starting with DCE3 hardware, atom contains a general purpose ProcessI2cChannelTransaction similar to ProcessAuxChannelTransaction. Add an implementation using the atom tables for DCE3+ hardware. This should be a little less CPU intensive than bit banging and may work better in certain cases. Enable it by setting the radeon hw_i2c module parameter to 1. E.g., radeon.hw_i2c=1 on the kernel command line in grub. Signed-off-by:
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Jean Delvare authored
The VESA specification suggests a 2.2 ms timeout on DDC channels. Use exactly that (as the i915 driver does) instead of hard-coding a jiffy count. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Reviewed-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Jean Delvare authored
A udelay value of 20 leads to an I2C bus running at only 25 kbps. I2C devices can typically operate faster than this, 50 kbps should be fine for all devices (and compliant devices can always stretch the clock if needed.) FWIW, the vast majority of framebuffer drivers set udelay to 10 already. So set it to 10 in DRM drivers too, this will make EDID block reads faster. We might even lower the udelay value later if no problem is reported. Signed-off-by:
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Ilija Hadzic authored
copy_blit operation works only on integral number of pages so benchmarks shorter than one page size (4K) do not make sense v2: use RADEON_GPU_PAGE_SIZE instead of "magic" 1024 number and sweep sizes between 1 * <page_size> to 16K * <page_size> doubling the size in each iteration; we get the same coverage, as in the original benchmark, but guarantee integer multiples of page size v3: add whitespace between '*' operator per review received from zajec5@gmail.com Signed-off-by:Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by:
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Ilija Hadzic authored
R600/700 and Evergreen/NI blit code have a few redundant definitions in respective .c file. Move common definitions into a separate (new) .h file. Signed-off-by:
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