It's not always the case that clock is already available when sgtl5000
get probed at the first time, e.g. the clock is provided by CPU DAI
which may be probed after sgtl5000.  So let's defer the probe when
devm_clk_get() call fails and give it chance to try later.

It fixes the regression on imx28 since commit 9e13f345 (ASoC: sgtl5000:
Let the codec acquire its clock).

[    1.927637] sgtl5000 0-000a: Failed to get mclock: -2
[    1.934280] sgtl5000: probe of 0-000a failed with error -2
[    1.945906] mxs-sgtl5000 sound.13: ASoC: CODEC (null) not registered
[    1.953787] mxs-sgtl5000 sound.13: snd_soc_register_card failed (-517)
[    1.960865] platform sound.13: Driver mxs-sgtl5000 requests probe deferral
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>

SGTL5000_PLL_FRAC_DIV_MASK is used to mask bits 0-10 (11 bits in total) of
register CHIP_PLL_CTRL, so fix the mask to accomodate all this bit range.
Reported-by: Oskar Schirmer <oskar@scara.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org

According to the sgtl5000 reference manual, the default value of CHIP_SSS_CTRL
is 0x10.
Reported-by: Oskar Schirmer <oskar@scara.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org