- 24 Jun, 2021 14 commits
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Ville Syrjälä authored
Since the llb allocation has a fixed size, let's grab it before the potentially variable sized cfb. That should avoid some allocation failure cases once we allow different compression ratios for FBC1. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210610183237.3920-10-ville.syrjala@linux.intel.comReviewed-by:
José Roberto de Souza <jose.souza@intel.com>
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Ville Syrjälä authored
Write the cfb allocation loop as an actual loop instead of some hard to read goto thing. Signed-off-by:
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Ville Syrjälä authored
Declutter find_compression_limit() a bit by extracting intel_fbc_stolen_end(). Signed-off-by:
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Ville Syrjälä authored
Exctract the limit->register value conversion into a common helper. Signed-off-by:
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Ville Syrjälä authored
The limit++ for the 16bpp case is nonsense since the compression limit is always supposed to be power of two. Replace it with <<=1. Signed-off-by:
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Ville Syrjälä authored
No point in passing the mm node explicitly to find_compression_limit() since it's always the same node for the cfb. Signed-off-by:
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Ville Syrjälä authored
Not much point in dynamically allocating the line length buffer mm node that I can see. Just embed it directly like we do the for the cfb node. One less failure point to worry about. Signed-off-by:
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Ville Syrjälä authored
Extract the CFB (+LLB) programming into a separate function. Signed-off-by:
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Ville Syrjälä authored
Let's call the compression limit the limit. Signed-off-by:
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Ville Syrjälä authored
adls is supposed to use special buf trans tables. Add what's missing. v2: Drop the RBR/HBR table since it's the same as for tgl Signed-off-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
All the foo_get_buf_trans_hdmi() functions just return a single table. Remove the pointless wrappers. v2: Handle adl-p Signed-off-by:
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Ville Syrjälä authored
The jsl/ehl buf trans functions are needlessly complicated. Simplify them. Signed-off-by:
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Ville Syrjälä authored
EHL is supposed to use special buf trans values for eDP HBR2+. Add such a table. Signed-off-by:
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Lee Shawn C authored
This workaround is specific for a particular panel on Google chromebook project. When user space daemon enter idle state. It request adjust brightness to 0, turn backlight_enable signal off and keep eDP main link active. On general LCD, this behavior might not be a problem. But on this panel, its tcon would expect source to execute full eDP power off sequence after drop backlight_enable signal. Without eDP power off sequence. Even source try to turn backlight_enable signal on and restore proper brightness level. This panel is not able to light on again. This WA ignored the request from user space daemon to disable backlight_enable signal and keep it on always. When user space request kernel to turn eDP display off, kernel driver still can control backlight_enable signal properly. It would not impact standard eDP power off sequence. v2: 1. modify the quirk name and debug messages. 2. unregister backlight.power callback for specific device. v3: 1. modify debug output messages. 2. use DMI_EXACT_MATCH instead of DMI_MATCH. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Signed-off-by:Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by:
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- 23 Jun, 2021 13 commits
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Ville Syrjälä authored
The icl combo phy DP HBR2 is identical to the eDP HBR3 table. Get rid of one redundant copy. Signed-off-by:
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Ville Syrjälä authored
For some reason the dg1 buf trans tables have been stuffed into icl_get_combo_buf_trans_edp() which doesn't even get called on dg1. Split them out into a proper dg1 specific function, and also make sure we use the proper buf trans tables for DP as well as eDP. v2: Add the hobl stuff Reviewed-by:
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Ville Syrjälä authored
Give RKL its own get_buf_trans() func. v2: Drop the FIXME since the spec was clarified to indicate that TGL values are used for the HDMI/eDP cases. Reviewed-by: -
Ville Syrjälä authored
Split the hsw/bdw/skl/kbl get_buf_trans() functions into clean platform specific variants. Reviewed-by:
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Ville Syrjälä authored
Convert the get_buf_trans() functions into an encoder vfunc. Allows us to get rid of bunch of platform if-ladders. v2: Handle adl-p Reviewed-by:
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Ville Syrjälä authored
Store the default HDMI buf trans entry in struct intel_ddi_buf_trans so that it's next to the actual table. This let's us start ridding ourselves of some platofrm specifics in intel_ddi_hdmi_num_entries(). Reviewed-by:
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Ville Syrjälä authored
Raise the abstraction level of the get_buf_trans() functions a bit more by returning the whole wrapper intel_ddi_buf_trans struct. v2: Handle adl-p Reviewed-by:
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Ville Syrjälä authored
Add a small helper to get the buf trans entris+num_entries from the struct. Should avoid copy-paste errors in the platform specific get_buf_trans() functions. @@ identifier T, N; @@ - *N = T.num_entries; - return T.entries; + return intel_get_buf_trans(&T, N); @@ @@ is_hobl_buf_trans(...) { ... } + + static const union intel_ddi_buf_trans_entry * + intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries) + { + *num_entries = ddi_translations->num_entries; + return ddi_translations->entries; + } v2: Handle adl-p Reviewed-by: -
Ville Syrjälä authored
Put a wrapper struct around the buf trans tables so that we can declare the number of entries and default HDMI entry alongside the table. @wrap@ identifier old =~ "^.*translations.*"; fresh identifier new = "_" ## old; type T; @@ <... static const T - old + new [] = { ... }; + + static const struct intel_ddi_buf_trans old = { + .entries = new, + .num_entries = ARRAY_SIZE(new), + }; ...> @@ identifier wrap.old; @@ ( - ARRAY_SIZE(old) + old.num_entries | - old + old.entries ) @@ @@ union intel_ddi_buf_trans_entry { ... }; + +struct intel_ddi_buf_trans { + const union intel_ddi_buf_trans_entry *entries; + u8 num_entries; +}; v2: Handle adl-p Reviewed-by: -
Ville Syrjälä authored
Rename the dkl phy buf trans tables to follow the same naming pattern used by everyone else. v2: Handle adl-p Reviewed-by:
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Ville Syrjälä authored
In order to abstact the buf trans stuff let's wrap the platform specific structs into a union. v2: Handle adl-p Reviewed-by:
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Ville Syrjälä authored
All the other platforms handle the output_type stuff in their *_get_buf_trans() functions. Do the same for hsw/bdw/skl. Reviewed-by:
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Ville Syrjälä authored
Give the hsw/bdw/skl buf trans stuff a better namespace. Reviewed-by:
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- 22 Jun, 2021 1 commit
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Jani Nikula authored
Add a single point of truth for figuring out the primary/secondary crtc for bigjoiner instead of duplicating the magic pipe +/- 1 in multiple places. Also fix the pipe validity checks to properly take non-contiguous pipes into account. The current checks may theoretically overflow i915->pipe_to_crtc_mapping[pipe], albeit with a warning, due to fused off pipes, as INTEL_NUM_PIPES() returns the actual number of pipes on the platform, and the check is for INTEL_NUM_PIPES() == pipe + 1. Prefer primary/secondary terminology going forward. v2: - Improved abstractions for pipe validity etc. Fixes: 8a029c11 ("drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave") Fixes: d961eb20 ("drm/i915/bigjoiner: atomic commit changes for uncompressed joiner") Cc: Animesh Manna <animesh.manna@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
Manasi Navare <manasi.dl.navare@intel.com> Signed-off-by:
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- 21 Jun, 2021 5 commits
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Anusha Srivatsa authored
Load DMC v2.10 on ADLP. The release notes mention that this version enables few power savings features. v2: Add DMC_PATH() for ADLP (Lucas) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210621191415.29823-5-anusha.srivatsa@intel.com
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Anusha Srivatsa authored
ADLP requires us to load both Pipe A and Pipe B. Plug Pipe B loading support. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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Anusha Srivatsa authored
This patch adds Pipe A plumbing to the already existing parsing and loading functions which is taken care of in the prep patches. Adding MAX_DMC_FW to keep track for both Main and Pipe A DMC while loading the respective blobs. Also adding present field in dmc_info. s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add fw_info_matches_stepping() helper. CSR_PROGRAM() should now take the starting address of the particular blob (Main or Pipe) and not hardcode it. v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct. v3: Add a missing corner cases of stepping-substepping combination in fw_info_matches_stepping() helper. v4: Add macro for start_mmioaddr for V1 package. Simplify code in dmc_set_fw_offset (Lucas) Cc: Souza, Jose <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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Anusha Srivatsa authored
This is a prep patch for Pipe DMC plugging. Add dmc_info struct in intel_dmc to have all common fields shared between all DMC's in the package. Add DMC_FW_MAIN(dmc_id 0) to refer to the blob. v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose) Cc: Souza, Jose <jose.souza@intel.com> Signed-off-by:
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Kees Cook authored
intel_dp_vsc_sdp_unpack() was using a memset() size (36, struct dp_sdp) larger than the destination (24, struct drm_dp_vsc_sdp), clobbering fields in struct intel_crtc_state after infoframes.vsc. Use the actual target size for the memset(). Fixes: 1b404b7d ("drm/i915/dp: Read out DP SDPs") Cc: stable@vger.kernel.org Signed-off-by:
Kees Cook <keescook@chromium.org> Reviewed-by:
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- 16 Jun, 2021 2 commits
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Imre Deak authored
Disconnect TypeC PHYs during system suspend and shutdown, even with the corresponding TypeC sink still plugged to its connector, since leaving the PHY connected causes havoc at least during system resume in the presence of an Nvidia card. Note that this will only make a difference in the TypeC DP alternate mode, since in Thunderbolt alternate mode the PHY is never owned by the display engine and there is no notion of PHY ownership in legacy mode (the display engine being the only possible owner in that mode and the TypeC subsystem not having anything to do with the port in that case). Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3500Reported-and-tested-by:
Chris Chiu <chris.chiu@canonical.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210610174223.605904-1-imre.deak@intel.com
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Tejas Upadhyay authored
When pipe A is disabled and MIPI DSI is enabled on pipe B, the AMT KVMR feature will incorrectly see pipe A as enabled. Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave it set while DSI is enabled on pipe B. No impact to setting it all the time. Changes since V5: - Added reviewed-by - Removed redundant braces and debug message format - Imre Changes since V4: - Modified function comment Wa_<number>:icl,jsl,ehl - Lucas - Modified debug message in sync state - Imre Changes since V3: - More meaningful name to workaround - Imre - Remove boolean check clear flag - Add WA_verify hook in dsi sync_state Changes since V2: - Used REG_BIT, ignored pipe A and used sw state check - Jani - Made function wrapper - Jani Changes since V1: - ./dim checkpatch errors addressed Signed-off-by:Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210615105613.851491-1-tejaskumarx.surendrakumar.upadhyay@intel.com
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- 14 Jun, 2021 1 commit
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Lucas De Marchi authored
It's becoming pretty cumbersome to track the features enabled going back to GEN7. Gather the XE_LPD display features together in XE_LPD_FEATURES macro so they are sufficient to describe the display features. In ADL-P's device_info we set has_psr_hw_tracking to 0 as it would otherwise be enabled since it is inheriting from GEN12_FEATURES. Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210612053531.1870920-1-lucas.demarchi@intel.com
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- 11 Jun, 2021 1 commit
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José Roberto de Souza authored
Looks this FIXME is still valid as we need a way to tell LSPCON to stop sending infoframes, so reverting it. This reverts commit 3f409e4c. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 10 Jun, 2021 1 commit
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Emil Velikov authored
Currently as the workaround is applied the screen flickers. As a result we do not achieve seamless boot experience. Avoiding the issue in the common use-case might be hard, although we can resolve it for dual GPU setups - when the "other" GPU is primary and/or outputs are connected to it. With this I was able to get seamless experience on my Intel/Nvidia box, running systemd-boot and sddm/Xorg. Note that the i915 driver is within initrd while the Nvidia one is not. Without this patch, the splash presented by systemd-boot (UEFI BGRT) is torn down as the code-path kicks in, leaving the monitor blank until the login manager starts. Same issue were reported with plymouth/grub, although personally I wasn't able to get them to behave on my setup. Suggested-by:
Emil Velikov <emil.velikov@collabora.com> Signed-off-by:
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- 09 Jun, 2021 2 commits
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Stanislav Lisovskiy authored
We currently treat same slice mask as a same DBuf state and skip updating the Dbuf slices, if we detect that. This is wrong as if we have a multi to single pipe change or vice versa, that would be treated as a same Dbuf state and thus no changes required, so we don't get Mbus updated, causing issues. Solution: check also mbus_join, in addition to slices mask. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
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Stanislav Lisovskiy authored
CDCLK crawl feature allows to change CDCLK frequency without disabling the actual PLL and doesn't require a full modeset. v2: - Added has_cdclk_crawl as a feature flag to intel_device_info(Matt Roper) - s/gen13_cdclk_pll_crawl/adlp_cdclk_pll_crawl/ (Matt Roper) Cc: Mika Kahola <mika.kahola@intel.com> Reviewed-by:Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
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