- 01 Dec, 2021 35 commits
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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George Shen authored
[Why] Certain display configurations require an extra delay before reading lane status with certain LTTPR. [How] Add temporary workaround to force AUX RD interval to 16ms for CR and EQ. Needs to be refactored later. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
George Shen <George.Shen@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Allow changing DET size with debug flag for testing purposes Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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George Shen authored
[Why] Vendor specific link rate toggle workaround should not be applied outside of link training scenario, such as when outputting PHY test pattern. [How] Add flag to indicate when link training is occuring. Make workaround a no-op when flag is not set. Reviewed-by:
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George Shen authored
[Why] Certain LTTPR require special workarounds in order to comply with DP specifications. [How] Implement vendor specific sequences via DPCD writes to vendor-specific LTTPR registers. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Mikita Lipski authored
[why] Adding a debugfs to show PSR capability of the panel and the driver. To use: cat /sys/kernel/debug/dri/0/eDP-X/psr_capability Expected output: Sink support: no/yes Driver support: no/yes [how] Adding psr_capability to eDP connectors. Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Tested-by:
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Brandon Syu authored
[WHY] Driver use primary eDP link stream as the condition to enable fastboot or not. In dual eDP case, set second screen only, this would cause slave eDP timing to be used on primary one. [HOW] Add a check for unmatched eDP link stream. Reviewed-by:
Brandon Syu <Brandon.Syu@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] Certain USB4 docks do not seem to be able to handle disabling DSC once it has been enabled on an MST stream. This can result in blank displays. [How] As a work around, always enable DSC on docks exhibiting this issue. The flag to indicate the use of DSC for MST streams on a USB4 dock is set during detection of the dock and only cleared when the USB4 dock is disconnected. Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
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Evgenii Krasnikov authored
[HOW&WHY] Add function to be used for early eDP power on Reviewed-by:
Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Tested-by:
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Mustapha Ghaddar authored
[WHY] It seems like after a series of plug/unplugs we end up in a situation where tiled display doesnt support Audio. [HOW] The issue seems to be related to when we check streams changed after an HPD, we should be checking the audio_struct as well to see if any of its values changed. Reviewed-by:
Mustapha Ghaddar <mustapha.ghaddar@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] During otg sync trigger, plane states are used to decide whether the otg is already synchronized or not. There are scenarions when otgs are disabled without plane state getting disabled and in such case the otg is excluded from synchronization. [How] Introduced pipe_idx_syncd in pipe_ctx that tracks each otgs master pipe. When a otg is disabled/enabled, pipe_idx_syncd is reset to itself. On sync trigger, pipe_idx_syncd is checked to decide whether a otg is already synchronized and the otg is further included or excluded from synchronization. Reviewed-by:
meenakshikumar somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Shen, George authored
[Why] VS and PE requested by repeater should not persist for the sink. [How] Clear DPCD lane settings after repeater link training finishes. Reviewed-by:
Wesley Chalmers <wesley.chalmers@amd.com> Acked-by:
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Dale Zhao authored
[Why] Using the hdmi_disable option doesnt disable 6GB bandwidth [How] Add debug.hdmi20_disable flage when checking 6GB enable or not. Reviewed-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Dale Zhao <dale.zhao@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] When trying to lightup two 4k60 non-DSC displays behind a branch device that supports DSC we can't lightup both at once due to bandwidth limitations - each requires 48 VCPI slots but we only have 63. [How] The workaround already exists in the code but is guarded by a CONFIG that cannot be set by the user and shouldn't need to be. Check for specific branch device IDs to device whether to enable the workaround for multiple display scenarios. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Stylon Wang authored
[Why + How] Enable P010 for SDR video applications. Reviewed-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
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Fangzhi Zuo authored
Change since v1: add brief description 1. Add hdmi frl pcon support to existing asic family. 2. Determine pcon frl capability based on pcon dpcd. 3. pcon frl is taken into consideration into mode validation. v2: squash in warning fix (Alex) Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Fangzhi Zuo authored
1. Parse DSC caps from PCON DPCD 2. Policy determins if DSC is decoded at PCON 3. Enable/disable DSC at PCON Signed-off-by:
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Lijo Lazar authored
On aldebaran, RLC also controls GFXCLK. Skip halting RLC during GFX IP suspend and keep it running till PMFW disables all DPMs. [ 578.019986] amdgpu 0000:23:00.0: amdgpu: GPU reset begin! [ 583.245566] amdgpu 0000:23:00.0: amdgpu: Failed to disable smu features. [ 583.245621] amdgpu 0000:23:00.0: amdgpu: Fail to disable dpm features! [ 583.245639] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]] *ERROR* suspend of IP block <smu> failed -62 [ 583.248504] [drm] free PSP TMR buffer Signed-off-by:Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lijo Lazar authored
HW_ID_MAX considers HWID of all IPs, far more than what amdgpu uses. amdgpu tracks only the IPs defined by amd_hw_ip_block_type whose max is MAX_HWIP. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Guchun Chen authored
There is no base reg offset or ip_version set for SDMA2 and SDMA3 on SIENNA_CICHLID, so add them. Signed-off-by:
Kevin Wang <kevinyang.wang@amd.com> Signed-off-by:
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Guchun Chen authored
>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:503:6: warning: no previous prototype for function 'release_psp_cmd_buf' [-Wmissing-prototypes] void release_psp_cmd_buf(struct psp_context *psp) ^ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:503:1: note: declare 'static' if the function is not intended to be used outside of this translation unit void release_psp_cmd_buf(struct psp_context *psp) ^ static 1 warning generated. Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
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Darren Powell authored
After modifying navi10 in previous commit, extend the changes so all implementations of pp_hwmgr_func->get_power_profile_mode and pptable_funcs->get_power_profile_mode use amdgpu_pp_profile_name == Test == LOGFILE=pp_profile_strings.test.log AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" > $LOGFILE FILES="pp_power_profile_mode " for f in $FILES do echo === $f === >> $LOGFILE cat $HWMON_DIR/device/$f >> $LOGFILE done cat $LOGFILE Signed-off-by:Darren Powell <darren.powell@amd.com> Reviewed-by:
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Darren Powell authored
== Description == All the power profile modes use the same strings (or a subset of) Creating a public array of the strings will allow sharing rather than duplicating for each chip First patch only implements change for navi10, followup with other chips == Changes == Create a declaration of the public array in kgd_pp_interface.h Define the public array in amdgpu_pm.c Modify the implementaiton of navi10_get_power_profile_mode to use new array == Test == LOGFILE=pp_profile_strings.test.log AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" > $LOGFILE FILES="pp_power_profile_mode " for f in $FILES do echo === $f === >> $LOGFILE cat $HWMON_DIR/device/$f >> $LOGFILE done cat $LOGFILE Signed-off-by: -
Philip Yang authored
IH ring1 is used to process GPU retry fault, overflow is enabled to drain retry fault because we want receive other interrupts while handling retry fault to recover range. There is no overflow flag set when wptr pass rptr. Use timestamp of rptr and wptr to handle overflow and drain retry fault. If fault timestamp goes backward, the fault is filtered and should not be processed. Drain fault is finished if processed_timestamp is equal to or larger than checkpoint timestamp. Add amdgpu_ih_functions interface decode_iv_ts for different chips to get timestamp from IV entry with different iv size and timestamp offset. amdgpu_ih_decode_iv_ts_helper is used for vega10, vega20, navi10. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Stanley.Yang authored
v2: still need call ras_disable_all_featrures to handle ras initilization failure case. Function amdgpu_device_fini_hw is called before amdgpu_device_fini_sw, so ras ta will unload before send ras disable command, ras dsiable operation must before hw fini. Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Lijo Lazar authored
v1: Ideally power gate/ungate requests shouldn't come when smu block is uninitialized. Add a WARN message to check the origins if such a thing ever happens. v2: Use dev_WARN to log device info (Felix/Guchun). Signed-off-by:
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Flora Cui authored
since vkms support atomic KMS interface Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Alex Deucher <aleander.deucher@amd.com> Reviewed-by:
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Flora Cui authored
otherwise adev->mode_info.crtcs[] is NULL Signed-off-by:
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Flora Cui authored
Signed-off-by:
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Christophe JAILLET authored
The 'doorbell_bitmap' bitmap has just been allocated. So we can use the non-atomic '__set_bit()' function to save a few cycles as no concurrent access can happen. Reviewed-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Christophe JAILLET authored
'doorbell_bitmap' and 'queue_slot_bitmap' are bitmaps. So use 'bitmap_zalloc()' to simplify code, improve the semantic and avoid some open-coded arithmetic in allocator arguments. Also change the corresponding 'kfree()' into 'bitmap_free()' to keep consistency. Reviewed-by:
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Lv Ruyi authored
Both of split and merge are pointers, not arrays. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Lv Ruyi <lv.ruyi@zte.com.cn> Signed-off-by:
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Jane Jian authored
[WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Reviewed-by:
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Jiapeng Chong authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c:96:14-15: WARNING comparing pointer to 0. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] PSR currently relies on the kernel's delayed vblank on/off mechanism as an implicit bufferring mechanism to prevent excessive entry/exit. Without this delay the user experience is impacted since it can take a few frames to enter/exit. [How] Only allow vblank disable immediate for DC when psr is not supported. Leave a TODO indicating that this support should be extended in the future to delay independent of the vblank interrupt. Fixes: 92020e81 ("drm/amdgpu/display: set vblank_disable_immediate for DC") Acked-by:
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- 24 Nov, 2021 5 commits
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Alex Deucher authored
Update the bios scratch register when updating the backlight level. Some platforms apparently read this scratch register and do additional operations in their hotkey handlers. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1518Reviewed-by:
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Alex Deucher authored
The overclocking interface currently appends data to a string. Revert back to using sprintf(). Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1774 Fixes: 6db0c87a ("amdgpu/pm: Replace hwmgr smu usage of sprintf with sysfs_emit") Acked-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Lijo Lazar authored
There is no need for additional programming, keep the default settings. Signed-off-by:
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Yang Wang authored
fix some byteorder issues about amdgpu discovery. This will result in running errors on the big end system. (e.g:MIPS) Signed-off-by:
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Philip Yang authored
If xnack is on, VM retry fault interrupt send to IH ring1, and ring1 will be full quickly. IH cannot receive other interrupts, this causes deadlock if migrating buffer using sdma and waiting for sdma done while handling retry fault. Remove VMC from IH storm client, enable ring1 write pointer overflow, then IH will drop retry fault interrupts and be able to receive other interrupts while driver is handling retry fault. IH ring1 write pointer doesn't writeback to memory by IH, and ring1 write pointer recorded by self-irq is not updated, so always read the latest ring1 write pointer from register. Signed-off-by:
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