- 07 Apr, 2017 2 commits
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Martin Blumenstingl authored
The NAND DQS pins are currently named nand_dqs_0 and nand_dqs_1. However, they both seem to have the same function, just exposed on different pins (unlike the ethernet TX pins for example, where there's eth_txd0..3 - all of these can be active at the same time as they are different data lines). Rename the NAND DQS pins to nand_dqs_15 and nand_dqs_18 to reflect that it's the same functionality just exposed on different pins (BOOT_15 and BOOT_18). Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Martin Blumenstingl authored
The nand_groups table uses different names for the NAND DQS pins than the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0). This prevents using the NAND DQS pins in the devicetree. Fix this by ensuring that the GROUP() definition and the meson8b_cbus_groups use the same name for these pins. Fixes: 0fefcb68 ("pinctrl: Add support for Meson8b") Signed-off-by:
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- 04 Apr, 2017 1 commit
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.12 (take two) - Add basic support for the Pin Function Controller on revision ES2.0 of the R-Car H3 SoC, which differs from ES1.x in many ways.
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- 30 Mar, 2017 3 commits
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Geert Uytterhoeven authored
Add pins, groups, and a function for SCIF_CLK on R-Car H3 ES2.0. SCIF_CLK is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF serial ports. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
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Geert Uytterhoeven authored
Add pins, groups, and functions for all SCIF serial ports on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: -
Geert Uytterhoeven authored
The Pin Function Controller module in the R-Car H3 ES2.0 differs from ES1.x in many ways. The goal is twofold: 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary for now, 2. Make it clear which code supports ES1.x, so it can easily be identified and removed later, when production SoCs are deemed ubiquitous. Hence this patch: 1. Extracts the support for R-Car H3 ES1.x into a separate file, as the differences are quite large, 2. Adds code for detecting the SoC revision at runtime using the new soc_device_match() API, and selecting pinctrl tables for the actual SoC revision, 3. Replaces the core register and bitfield definitions by their counterparts for R-Car H3 ES2.0. The addition of pins, groups, and functions for the various on-chip devices is left to subsequent patches. The R-Car H3 ES2.0 register and bitfield definitions were extracted from a patch in the BSP by Takeshi Kihara. Signed-off-by:
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- 28 Mar, 2017 11 commits
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Jerome Brunet authored
Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
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Jerome Brunet authored
Signed-off-by:
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Jerome Brunet authored
Signed-off-by:
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Jerome Brunet authored
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Neil Armstrong authored
When trying to add a gpio-hog, we enter a weird loop where the gpio-ranges is needed when gpiochip_add_data() is called but in the current implementation the ranges are added from the driver afterwards. A simple solution is to rely on the DR gpio-ranges attribute and remove the call to gpiochip_add_pin_range(). Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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Krzysztof Kozlowski authored
Add a Git tree on @kernel.org for maintaining the Samsung pinctrl drivers. The tree will be maintained in a shared model between current Samsung pinctrl maintainers. Pull requests will be going to Linus Walleij. Also add the patchwork for linux-samsung-soc mailing list which will be used for handling the patches. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Acked-by:
Tomasz Figa <tomasz.figa@gmail.com> Acked-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
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Neil Armstrong authored
Fix some inverted bit numbers in some pinctrl groups and add missing pins and groups to be in pair with the GXBB pinctrl pins definition. Signed-off-by:
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John Keeping authored
With real-time preemption, regmap functions cannot be used in the implementation of irq_chip since they use spinlocks which may sleep. Move the setting of the mux for IRQs to an irq_bus_sync_unlock handler where we are allowed to sleep. Signed-off-by:
John Keeping <john@metanate.com> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
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John Keeping authored
We need to avoid calling regmap functions from irq handlers, so the next commit is going to move the call to rockchip_set_mux() into an irq_bus_sync_unlock handler. But we can't return an error from there so we still need to check the settings from rockchip_irq_set_type() and we will use this new rockchip_verify_mux() function from there. Signed-off-by:
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John Keeping authored
This lock is used from rockchip_irq_set_type() which is part of the irq_chip implementation and thus must use raw_spinlock_t as documented in Documentation/gpio/driver.txt. Signed-off-by:
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John Keeping authored
regmap_update_bits does its own locking and everything else accessed here is a local variable so there is no need to lock around it. Signed-off-by:
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- 24 Mar, 2017 1 commit
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.12 - Fixes and cleanups.
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- 23 Mar, 2017 7 commits
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Hans de Goede authored
On some Cherry Trail devices the ASL uses the GMMR GPIO to access GPIOs so as to serialize MMIO accesses to GPIO registers with the OS, because: "Due to a silicon issue, a shared lock must be used to prevent concurrent accesses across the 4 GPIO controllers. See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), errata #CHT34, for further information." This commit adds support for this opregion, this fixes a number of ASL errors on my Ezpad mini3 tablet and makes the otg port device/host muxing which is controlled in firmware on this model work properly. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Andy Yan authored
Rockchip finally named the SOC as RV1108, so change it. Signed-off-by:
Andy Yan <andy.yan@rock-chips.com> [adapted rk1108 dtsi to keep bisectability] Signed-off-by:
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Andy Yan authored
Rockchip finally named the SOC as RV1108, so change it. Also move the compatible list to one compatible per line. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Jeffy Chen authored
Currently we are trying to enable/disable the clk of irq's gpio bank when unmask/mask irq. But the kernel's "lazy disable approach" will skip masking irq when the irq chip doesn't support irq_disable ops. So we may hit this case: irq_enable-> enable clk irq_disable-> noop irq_enable-> enable clk again irq_disable-> noop Signed-off-by:
Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by:
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Masahiro Yamada authored
At first these drivers were written as tristate, but the module usecases are actually not tested. Make all of them boolean. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Masahiro Yamada authored
Since commit 3e030b0b ("pinctrl: uniphier: allow to have pinctrl node under syscon node"), this driver has kept compatibility for the old DT files. Several releases have passed since then, so remove the obsoleted compatibles and clean up the code. Signed-off-by:
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Martin Blumenstingl authored
This adds support for the missing PWM pins on Meson GXL SoCs, namely: - PWM_A - PWM_B - PWM_C - PWM_F (GPIOX_7 and GPIOCLK_1 can be selected as output) - PWM_AO_A (GPIOAO_3 and GPIOAO_8 can be selected as output) Signed-off-by:
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- 21 Mar, 2017 3 commits
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Geert Uytterhoeven authored
Update the sh_pfc_soc_info pointer after calling the SoC-specific initialization function, as it may have been updated to e.g. handle different SoC revisions. This makes sure the correct subdriver name is printed later. Fixes: 0c151062 ("sh-pfc: Add support for SoC-specific initialization") Signed-off-by:
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Geert Uytterhoeven authored
Somehow the QSPI and SCIF_CLK fragments were inserted at the wrong positions. Restore sort order (alphabetically, per group). Signed-off-by: -
Geert Uytterhoeven authored
Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[]. Fixes: a56069c4 ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions") Signed-off-by:
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- 16 Mar, 2017 5 commits
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Julia Cartwright authored
The sunxi pinctrl driver currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
Julia Cartwright <julia@ni.com> Signed-off-by:
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Julia Cartwright authored
The sirf atlas7 pinctrl drivers currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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Julia Cartwright authored
The amd pinctrl drivers currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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Julia Cartwright authored
The bcm pinctrl drivers currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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Timur Tabi authored
The sysfs and debugfs entries for pin control drivers work better when the individual pins are given real names, even if they are all just "gpio0", "gpio1", etc. Signed-off-by:
Timur Tabi <timur@codeaurora.org> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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- 14 Mar, 2017 7 commits
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david.wu authored
Signed-off-by:
David Wu <david.wu@rock-chips.com> Reviewed-by:
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david.wu authored
To prevent external signal crosstalk, some pins need to enable input schmitt, like i2c pins, 32k-input pin and so on. Signed-off-by:
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Icenowy Zheng authored
Allwinner pin controllers are also GPIO controllers. Currently, if GPIOLIB is forgot to be chosen, the build of pinctrl-sunxi.c will fail for lacking a lot of gpiochip_* functions. Select GPIOLIB to ensure this driver can be built. Signed-off-by:
Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by:
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Icenowy Zheng authored
The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC. Add support for the pins controlled by the R_PIO controller. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Icenowy Zheng authored
Allwinner A64 SoC has also a dedicated pin controller for Port L GPIOs, which is called "Port Controller (CPUs-PORT)" in SoC User Manual. Add a binding for this pin controller, like the ones in A23/33 and H3. Signed-off-by:
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Icenowy Zheng authored
The compatible for Allwinner H5 pin controller is wrong written as allwinner,sun50i-h5-r-pinctrl, however, it's really a generic pinctrl rather than a "r" one. Fix this compatible string. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Icenowy Zheng authored
ARM64 Allwinner SoCs used to have every pinctrl driver selected in ARCH_SUNXI. Change this to make their default value to (ARM64 && ARCH_SUNXI). Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Acked-by:
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