- 21 Feb, 2024 1 commit
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Krzysztof Kozlowski authored
Use proper model name in SM8650 LPASS pin controller Kconfig entry. Cc: <stable@vger.kernel.org> Fixes: c4e47673 ("pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240216102435.89867-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 13 Feb, 2024 1 commit
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.9 - Add pin groups for SCIF_CLK2 on R-Car V4H, - Add support for port pins P19 to P28 on RZ/Five, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 09 Feb, 2024 3 commits
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Arturas Moskvinas authored
GPINTEN register contains information about GPIOs with enabled interrupts no need to check other GPIOs for changes. Signed-off-by: Arturas Moskvinas <arturas.moskvinas@gmail.com> Link: https://lore.kernel.org/r/20240201141406.32484-2-arturas.moskvinas@gmail.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Naresh Solanki authored
Update maxItems to 60 for gpio-reserved-ranges to allow multiple gpio reserved ranges. Add input-enable property to allow configuring a pin as input. Also update example. Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240206112501.715042-1-naresh.solanki@9elements.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Rob Herring authored
The structure of the NVIDIA Tegra234 common pinmux schema doesn't work for restricting properties because a child node schema can't be extended with additional properties from another schema defining the same child node. The 2 child node schemas are evaluated independently as the schemas are not recursively combined in any way. As the common schema is almost all the child node schema anyways, just remove the parent node from the common schema. Then add 'reg' and adjust the $ref's in the users of the common schema. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240202223454.1667383-1-robh@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 07 Feb, 2024 3 commits
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Chen-Yu Tsai authored
The MT8192 does not support configuring pin slew rate. This is evident from both the datasheet, and the fact that the driver points the slew rate register range at the GPIO direction register range. Drop the bogus setting. Fixes: d32f38f2 ("pinctrl: mediatek: Add pinctrl driver for mt8192") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240131071910.3950450-2-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Chen-Yu Tsai authored
The MT8186 does not support configuring pin slew rate. This is evident from both the datasheet, and the fact that the driver points the slew rate register range at the GPIO direction register range. Drop the bogus setting. Fixes: 8b483bda ("pinctrl: add pinctrl driver on mt8186") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240131071910.3950450-1-wenst@chromium.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Andy Shevchenko authored
There is no modifications are assumed for wpcm450_groups. Constify it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211154239.4190429-1-andriy.shevchenko@linux.intel.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 31 Jan, 2024 12 commits
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Lad Prabhakar authored
Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins provide expanded capabilities and are exclusive to the RZ/Five SoC. Couple of port pins have different configuration and are not identical for the complete port so introduce struct rzg2l_variable_pin_cfg to handle such cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config is then assigned in rzg2l_pinctrl_get_variable_pin_cfg(). Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins which support interrupt facility. While at define RZG2L_GPIO_PORT_PACK() using RZG2L_GPIO_PORT_SPARSE_PACK(). Update the gpio-ranges property in the RZ/Five SoC DTSI, as it must match the driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240129135556.63466-4-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20240129135556.63466-5-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Lad Prabhakar authored
Currently we assume all the port pins are sequential ie always PX_0 to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to P28_5 which have holes in them, for example only one pin on port19 is available and that is P19_1 and not P19_0. So to handle such cases include pinmap for each port which would indicate the pin availability on each port. As the pincount can be calculated based on pinmap drop this from RZG2L_GPIO_PORT_PACK() macro. Previously we had a max of 7 pins on each port but on RZ/Five Port-20 has 8 pins, so move the single pin configuration to BIT(63). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240129135556.63466-3-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Lad Prabhakar authored
As the RZ/G2L pinctrl driver is extensively utilized by numerous SoCs and has experienced substantial growth, enhance code readability by incorporating FIELD_PREP_CONST/FIELD_GET macros wherever necessary. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240129135556.63466-2-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
If the number of provided enum IDs in a variable width config register description does not match the expected number, the checker uses the expected number for validating the individual enum IDs. However, this may cause out-of-bounds accesses on the array holding the enum IDs, leading to bogus enum_id conflict warnings. Worse, if the bug is an incorrect bit field description (e.g. accidentally using "12" instead of "-12" for a reserved field), thousands of warnings may be printed, overflowing the kernel log buffer. Fix this by limiting the enum ID check to the number of provided enum IDs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c7385f44f2faebb8856bcbb4e908d846fc1531fb.1705930809.git.geert+renesas@glider.be
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Geert Uytterhoeven authored
R-Car V4H actually has two SCIF_CLK pins. The second pin provides the SCIF_CLK signal for HSCIF2 and SCIF4. Fixes: 050442ae ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6352ec9b63fdd38c2c70d8d203e46f21fbfeccdc.1705589612.git.geert+renesas@glider.be
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Claudiu Beznea authored
Commit d3aaa720 ("pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups") introduced the possibility to parse pin configuration for pinmux groups. It did that by calling rzg2l_map_add_config() at the end of rzg2l_dt_subnode_to_map() and jumping to the remove_group label in case rzg2l_map_add_config() failed. But if that happens, the mutex will already be unlocked, thus this it will lead to double mutex unlock operation. To fix this move the rzg2l_map_add_config() call just after all the name argument is ready and before the mutex is locked. There is no harm in doing this, as this only parses the data from device tree that will be further processed by pinctrl core code. Fixes: d3aaa720 ("pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/f8c3a3a0-7c48-4e40-8af0-ed4e9d9b049f@moroto.mountainSigned-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240115153453.99226-1-claudiu.beznea.uj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Michal Simek authored
Compatible string doesn't really match with compatible string listed in the driver itself. While binding was converted from txt to yaml xlnx,zynq-pinctrl was listed as compatible string but example was using xlnx,pinctrl-zynq and also this string is used in all DTSes. xlnx,zynq-pinctrl is used only in dt binding and not present in any DT which is stable for quite a long time that's why use old compatible string and update binding document instead of starting to use unused compatible string. Fixes: 153df45a ("dt-bindings: pinctrl: pinctrl-zynq: Convert to yaml") Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/c1307a4dd5e30290acacc786cb2170deb9eaa539.1706087258.git.michal.simek@amd.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Charles Keepax authored
Use str_high_low() rather than open coding. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240129153138.3221604-3-ckeepax@opensource.cirrus.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Charles Keepax authored
Remove some pointless inline declarations, no reason not to let the compiler decide. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240129153138.3221604-2-ckeepax@opensource.cirrus.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Charles Keepax authored
Fixup a couple of incorrect header includes. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240129153138.3221604-1-ckeepax@opensource.cirrus.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Rob Herring authored
pincfg-node.yaml already defines the type for "slew-rate", so drop the type from the nuvoton,npcm845-pinctrl binding. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240124190106.1540585-2-robh@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Rob Herring authored
nuvoton,npcm845-pinctrl defines the common "input-debounce" property as an array rather than an scalar. Update the common definition to expand it to an uint32-array, and update all the users of the property with array constraints. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240124190106.1540585-1-robh@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 28 Jan, 2024 2 commits
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Krzysztof Kozlowski authored
Regular expression used to match the unit address part should not allow non-hex numbers. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240123083511.21063-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Erick Archer authored
As noted in the "Deprecated Interfaces, Language Features, Attributes, and Conventions" documentation [1], size calculations (especially multiplication) should not be performed in memory allocator (or similar) function arguments due to the risk of them overflowing. This could lead to values wrapping around and a smaller allocation being made than the caller was expecting. Using those allocations could lead to linear overflows of heap memory and other misbehaviors. So, use the purpose specific devm_kcalloc() function instead of the argument size * count in the devm_kzalloc() function. Link: https://www.kernel.org/doc/html/next/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments [1] Link: https://github.com/KSPP/linux/issues/162Signed-off-by: Erick Archer <erick.archer@gmx.com> Acked-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20240119181909.7079-1-erick.archer@gmx.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 27 Jan, 2024 4 commits
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Jean Thomas authored
Add new emmc groups in the pinctrl driver for the MediaTek MT7981 SoC: * emmc reset, with pin 15. * emmc 4-bit bus-width, with pins 16 to 19, and 24 to 25. * emmc 8-bit bus-width, with pins 16 to 25. The existing emmc_45 group is kept for legacy reasons, even if this is the union of emmc_reset and emmc_8 groups. Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr> Reviewed-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20240117145547.3354242-1-jean.thomas@wifirst.frSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Jean Thomas authored
Add uart1_3 (pins 26, 27) group to the pinctrl driver for the MediaTek MT7981 SoC. Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr> Reviewed-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20240117124234.3137050-1-jean.thomas@wifirst.frSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Randy Dunlap authored
Fix kernel-doc warnings for enum (anonymous): the enum values are not documented, so don't indicate that the comment contains kernel-doc notation. pinctrl-mt7986.c:68: warning: Enum value 'GPIO_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_RT_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_RB_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_LT_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_LB_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_TR_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_TL_BASE' not described in enum '(anonymous)' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312110210.x3vxq42A-lkp@intel.com/ Cc: Linus Walleij <linus.walleij@linaro.org> Cc: <linux-gpio@vger.kernel.org> Cc: Sean Wang <sean.wang@kernel.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: <linux-mediatek@lists.infradead.org> Cc: <linux-arm-kernel@lists.infradead.org> Link: https://lore.kernel.org/r/20240111045126.13768-1-rdunlap@infradead.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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Chen Ni authored
Return pinctrl_gpio_direction_output() in order to transfer the error if it fails. Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240103085058.3771653-1-nichen@iscas.ac.cnSigned-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 21 Jan, 2024 14 commits
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Linus Torvalds authored
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https://evilpiepirate.org/git/bcachefsLinus Torvalds authored
Pull more bcachefs updates from Kent Overstreet: "Some fixes, Some refactoring, some minor features: - Assorted prep work for disk space accounting rewrite - BTREE_TRIGGER_ATOMIC: after combining our trigger callbacks, this makes our trigger context more explicit - A few fixes to avoid excessive transaction restarts on multithreaded workloads: fstests (in addition to ktest tests) are now checking slowpath counters, and that's shaking out a few bugs - Assorted tracepoint improvements - Starting to break up bcachefs_format.h and move on disk types so they're with the code they belong to; this will make room to start documenting the on disk format better. - A few minor fixes" * tag 'bcachefs-2024-01-21' of https://evilpiepirate.org/git/bcachefs: (46 commits) bcachefs: Improve inode_to_text() bcachefs: logged_ops_format.h bcachefs: reflink_format.h bcachefs; extents_format.h bcachefs: ec_format.h bcachefs: subvolume_format.h bcachefs: snapshot_format.h bcachefs: alloc_background_format.h bcachefs: xattr_format.h bcachefs: dirent_format.h bcachefs: inode_format.h bcachefs; quota_format.h bcachefs: sb-counters_format.h bcachefs: counters.c -> sb-counters.c bcachefs: comment bch_subvolume bcachefs: bch_snapshot::btime bcachefs: add missing __GFP_NOWARN bcachefs: opts->compression can now also be applied in the background bcachefs: Prep work for variable size btree node buffers bcachefs: grab s_umount only if snapshotting ...
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull timer updates from Thomas Gleixner: "Updates for time and clocksources: - A fix for the idle and iowait time accounting vs CPU hotplug. The time is reset on CPU hotplug which makes the accumulated systemwide time jump backwards. - Assorted fixes and improvements for clocksource/event drivers" * tag 'timers-core-2024-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: tick-sched: Fix idle and iowait sleeptime accounting vs CPU hotplug clocksource/drivers/ep93xx: Fix error handling during probe clocksource/drivers/cadence-ttc: Fix some kernel-doc warnings clocksource/drivers/timer-ti-dm: Fix make W=n kerneldoc warnings clocksource/timer-riscv: Add riscv_clock_shutdown callback dt-bindings: timer: Add StarFive JH8100 clint dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs
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git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linuxLinus Torvalds authored
Pull powerpc fixes from Aneesh Kumar: - Increase default stack size to 32KB for Book3S Thanks to Michael Ellerman. * tag 'powerpc-6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/64s: Increase default stack size to 32KB
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Kent Overstreet authored
Add line breaks - inode_to_text() is now much easier to read. Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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