1. 12 Jun, 2023 11 commits
  2. 10 Jun, 2023 23 commits
  3. 09 Jun, 2023 6 commits
    • Lee Jones's avatar
      net/sched: cls_u32: Fix reference counter leak leading to overflow · 04c55383
      Lee Jones authored
      In the event of a failure in tcf_change_indev(), u32_set_parms() will
      immediately return without decrementing the recently incremented
      reference counter.  If this happens enough times, the counter will
      rollover and the reference freed, leading to a double free which can be
      used to do 'bad things'.
      
      In order to prevent this, move the point of possible failure above the
      point where the reference counter is incremented.  Also save any
      meaningful return values to be applied to the return data at the
      appropriate point in time.
      
      This issue was caught with KASAN.
      
      Fixes: 705c7091 ("net: sched: cls_u32: no need to call tcf_exts_change for newly allocated struct")
      Suggested-by: default avatarEric Dumazet <edumazet@google.com>
      Signed-off-by: default avatarLee Jones <lee@kernel.org>
      Reviewed-by: default avatarEric Dumazet <edumazet@google.com>
      Acked-by: default avatarJamal Hadi Salim <jhs@mojatatu.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      04c55383
    • Zhengchao Shao's avatar
      net/sched: taprio: fix slab-out-of-bounds Read in taprio_dequeue_from_txq · be3618d9
      Zhengchao Shao authored
      As shown in [1], out-of-bounds access occurs in two cases:
      1)when the qdisc of the taprio type is used to replace the previously
      configured taprio, count and offset in tc_to_txq can be set to 0. In this
      case, the value of *txq in taprio_next_tc_txq() will increases
      continuously. When the number of accessed queues exceeds the number of
      queues on the device, out-of-bounds access occurs.
      2)When packets are dequeued, taprio can be deleted. In this case, the tc
      rule of dev is cleared. The count and offset values are also set to 0. In
      this case, out-of-bounds access is also caused.
      
      Now the restriction on the queue number is added.
      
      [1] https://groups.google.com/g/syzkaller-bugs/c/_lYOKgkBVMg
      Fixes: 2f530df7 ("net/sched: taprio: give higher priority to higher TCs in software dequeue mode")
      Reported-by: syzbot+04afcb3d2c840447559a@syzkaller.appspotmail.com
      Signed-off-by: default avatarZhengchao Shao <shaozhengchao@huawei.com>
      Tested-by: default avatarPedro Tammela <pctammela@mojatatu.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      be3618d9
    • Ratheesh Kannoth's avatar
      octeontx2-af: Fix promiscuous mode · c0e48937
      Ratheesh Kannoth authored
      CN10KB silicon introduced a new exact match feature,
      which is used for DMAC filtering. The state of installed
      DMAC filters in this exact match table is getting corrupted
      when promiscuous mode is toggled. Fix this by not touching
      Exact match related config when promiscuous mode is toggled.
      
      Fixes: 2dba9459 ("octeontx2-af: Wrapper functions for MAC addr add/del/update/reset")
      Signed-off-by: default avatarRatheesh Kannoth <rkannoth@marvell.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      c0e48937
    • Yoshihiro Shimoda's avatar
      net: renesas: rswitch: Fix timestamp feature after all descriptors are used · 0ad4982c
      Yoshihiro Shimoda authored
      The timestamp descriptors were intended to act cyclically. Descriptors
      from index 0 through gq->ring_size - 1 contain actual information, and
      the last index (gq->ring_size) should have LINKFIX to indicate
      the first index 0 descriptor. However, the LINKFIX value is missing,
      causing the timestamp feature to stop after all descriptors are used.
      To resolve this issue, set the LINKFIX to the timestamp descritors.
      Reported-by: default avatarPhong Hoang <phong.hoang.wz@renesas.com>
      Fixes: 33f5d733 ("net: renesas: rswitch: Improve TX timestamp accuracy")
      Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
      Reviewed-by: default avatarSimon Horman <simon.horman@corigine.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      0ad4982c
    • Max Tottenham's avatar
      net/sched: act_pedit: Parse L3 Header for L4 offset · 6c02568f
      Max Tottenham authored
      Instead of relying on skb->transport_header being set correctly, opt
      instead to parse the L3 header length out of the L3 headers for both
      IPv4/IPv6 when the Extended Layer Op for tcp/udp is used. This fixes a
      bug if GRO is disabled, when GRO is disabled skb->transport_header is
      set by __netif_receive_skb_core() to point to the L3 header, it's later
      fixed by the upper protocol layers, but act_pedit will receive the SKB
      before the fixups are completed. The existing behavior causes the
      following to edit the L3 header if GRO is disabled instead of the UDP
      header:
      
          tc filter add dev eth0 ingress protocol ip flower ip_proto udp \
       dst_ip 192.168.1.3 action pedit ex munge udp set dport 18053
      
      Also re-introduce a rate-limited warning if we were unable to extract
      the header offset when using the 'ex' interface.
      
      Fixes: 71d0ed70 ("net/act_pedit: Support using offset relative to
      the conventional network headers")
      Signed-off-by: default avatarMax Tottenham <mtottenh@akamai.com>
      Reviewed-by: default avatarJosh Hunt <johunt@akamai.com>
      Reported-by: default avatarkernel test robot <lkp@intel.com>
      Closes: https://lore.kernel.org/oe-kbuild-all/202305261541.N165u9TZ-lkp@intel.com/Reviewed-by: default avatarPedro Tammela <pctammela@mojatatu.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6c02568f
    • Wes Huang's avatar
      net: usb: qmi_wwan: add support for Compal RXM-G1 · 86319919
      Wes Huang authored
      Add support for Compal RXM-G1 which is based on Qualcomm SDX55 chip.
      This patch adds support for two compositions:
      
      0x9091: DIAG + MODEM + QMI_RMNET + ADB
      0x90db: DIAG + DUN + RMNET + DPL + QDSS(Trace) + ADB
      
      T:  Bus=03 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#=  2 Spd=5000 MxCh= 0
      D:  Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs=  1
      P:  Vendor=05c6 ProdID=9091 Rev= 4.14
      S:  Manufacturer=QCOM
      S:  Product=SDXPRAIRIE-MTP _SN:719AB680
      S:  SerialNumber=719ab680
      C:* #Ifs= 4 Cfg#= 1 Atr=80 MxPwr=896mA
      I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=(none)
      E:  Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      E:  Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      I:* If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=(none)
      E:  Ad=83(I) Atr=03(Int.) MxPS=  10 Ivl=32ms
      E:  Ad=82(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      E:  Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan
      E:  Ad=84(I) Atr=03(Int.) MxPS=   8 Ivl=32ms
      E:  Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      E:  Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=(none)
      E:  Ad=03(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      E:  Ad=85(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      
      T:  Bus=03 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#=  2 Spd=5000 MxCh= 0
      D:  Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs=  1
      P:  Vendor=05c6 ProdID=90db Rev= 4.14
      S:  Manufacturer=QCOM
      S:  Product=SDXPRAIRIE-MTP _SN:719AB680
      S:  SerialNumber=719ab680
      C:* #Ifs= 6 Cfg#= 1 Atr=80 MxPwr=896mA
      I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=(none)
      E:  Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      E:  Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      I:* If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=(none)
      E:  Ad=83(I) Atr=03(Int.) MxPS=  10 Ivl=32ms
      E:  Ad=82(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      E:  Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan
      E:  Ad=84(I) Atr=03(Int.) MxPS=   8 Ivl=32ms
      E:  Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      E:  Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      I:* If#= 3 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none)
      E:  Ad=8f(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      I:* If#= 4 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none)
      E:  Ad=85(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      I:* If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=(none)
      E:  Ad=03(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      E:  Ad=86(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
      
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarWes Huang <wes.huang@moxa.com>
      Acked-by: default avatarBjørn Mork <bjorn@mork.no>
      Link: https://lore.kernel.org/r/20230608030141.3546-1-wes.huang@moxa.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      86319919