- 13 Dec, 2022 1 commit
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Shikang Fan authored
- evict_resource is taking too long causing sriov full access mode timeout. So, add an extra evict_resource in the beginning as an early evict. Signed-off-by:
Shikang Fan <shikang.fan@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 09 Dec, 2022 7 commits
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Alex Deucher authored
Some special polaris 10 chips overlap with the polaris11 DID range. Handle this properly in the driver. v2: use local flags for other function calls. Acked-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Alex Deucher authored
Only apply the static threshold for Stoney and Carrizo. This hardware has certain requirements that don't allow mixing of GTT and VRAM. Newer asics do not have these requirements so we should be able to be more flexible with where buffers end up. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2270 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2291 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2255Acked-by:
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Colin Ian King authored
There is a spelling mistake in the struct field dram_clk_chanage. Fix it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.2-2022-12-07: amdgpu: - DSC fixes for DCN 2.1 - HDMI PCON fixes - PSR fixes - DC DML fixes - Properly throttle on BO allocation - GFX 11.0.4 fixes - MMHUB fix - Make some functions static Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221207232439.5908-1-alexander.deucher@amd.com
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.2-2022-12-02: amdgpu: - Fix CPU stalls when allocating large amounts of system memory - SR-IOV fixes - BACO fixes - Enable GC 11.0.4 - Enable PSP 13.0.11 - Enable SMU 13.0.11 - Enable NBIO 7.7.1 - Fix reported VCN capabilities for RDNA2 - Misc cleanups - PCI ref count fixes - DCN DPIA fixes - DCN 3.2.x fixes - Documentation updates - GC 11.x fixes - VCN RAS fixes - APU fix for passthrough - PSR fixes - GFX preemption support for gfx9 - SDMA fix for S0ix amdkfd: - Enable KFD support for GC 11.0.4 - Misc cleanups - Fix memory leak Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2022-12-08' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Some deferred-io and damage worker reworks revert and make a fb function static Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2022-12-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Multi-cast register fix (Matt) - Fix workarounds on gen2-3 (Tvrtko) - Bigjoiner fix (Ville) - Make Guc default_list a const data (Jani) - Acquire forcewake before uncore read (Umesh) - Selftest fix (Umesh) - HuC related fixes (Daniele) - Fix some incorrect return values (Janusz) - Fix a memory leak in bios related code (Xia) - Fix VBT send packet port selection (Mikko) - DG2's DMC fix bump for Register noclaims and few restore (Gustavo) Signed-off-by:
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- 06 Dec, 2022 22 commits
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Yang Wang authored
fix MMHUB register base coding error. Fixes: ec683759 ("drm/amdgpu/gmc10: program the smallK fragment size") Signed-off-by:
Yang Wang <KevinYang.Wang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Tim Huang authored
Add tmz support for GC 11.0.4. Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
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Tim Huang authored
Enable GFX IP v11.0.4 CG gate/ungate control. Signed-off-by:
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Tim Huang authored
Enable GFX Power Gating control for GC IP v11.0.4. Signed-off-by:
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Tim Huang authored
Add CG support for GFX/MC/HDP/ATHUB/IH/BIF. Signed-off-by:
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Jiadong Zhu authored
lkp robot reported missing-prototypes and unused-but-set-variable warnings on some functions of amdgpu_mcbp_mux.c. Make them static and remove the unused variable. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by:
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Christian König authored
We already fallback to a dummy BO with no backing store when we allocate GDS,GWS and OA resources and to GTT when we allocate VRAM. Drop all those workarounds and generalize this for GTT as well. This fixes ENOMEM issues with runaway applications which try to allocate/free GTT in a loop and are otherwise only limited by the CPU speed. The CS will wait for the cleanup of freed up BOs to satisfy the various domain specific limits and so effectively throttle those buggy applications down to a sane allocation behavior again. Signed-off-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] LinkCapacitySupport array is indexed with the number of voltage states and not the number of max DPPs. Fix the error by changing the array declaration to use the correct (larger) array size of total number of voltage states. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Aric Cyr authored
Acked-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Dillon Varone authored
[Description] When compressed buffer allocation changes, optimized required flag should be set to trigger an update in optimize bandwidth. Reviewed-by:
Dillon Varone <Dillon.Varone@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] It's currently tied to Z10 support, and is required for Z10, but we can still support Z10 display off without PSR. We currently need to skip the PSR CRTC disable to prevent stuttering and underflow from occuring during PSR-SU. [How] Add a debug option to allow specifying this separately. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Zhongwei authored
[Why] The input UrgentLatency in CalculateUrgentBurstFactor of prefect check is wrong. [How] Correct to the correct one to keep same as HW formula Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Zhongwei <Zhongwei.Zhang@amd.com> Tested-by:
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Charlene Liu authored
[why] HW register bit define changed. Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Alvin Lee authored
[Description] - Ensure dc_commit_streams returns the correct return code so any failures can be handled properly in DM layer - If set timings fail and we have to remove MPO planes, do so unconditionally but make sure to mark for removal so we report the VSYNC and prevent timeout - Failure to remove MPO plane results in set timings failure due to lack of resources Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Paul Hsieh authored
[Why] There is no DDC_6 pin on new asic cause the mapping table is incorrect. When app try to access DDC_VGA port, driver read an invalid ddc pin status and report engine busy. [How] Add dummy DDC_6 pin to align gpio structure. Reviewed-by:
Paul Hsieh <Paul.Hsieh@amd.com> Tested-by:
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Dillon Varone authored
[Description] If validating for max voltage level (therefore max clocks) always pass over the DET swath fill latency hiding check. Reviewed-by:
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Dillon Varone authored
[Description] When subvp is in use, main pipes should block unintended natural uclk pstate changes to prevent disruption to the state machine. Reviewed-by:
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Michael Strauss authored
[WHY] Low dscclk in high vlevels blocks some DSC modes. [HOW] Update dscclk to 1/3 of dispclk. Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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David Galiffi authored
[Why] It is not enabled for DCN3.0.1, 3.0.2, 3.0.3. [How] Add `dc->caps.dp_hdmi21_pcon_support = true` to these DCN versions. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
David Galiffi <David.Galiffi@amd.com> Tested-by:
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Dmytro Laktyushkin authored
Seamless boot requires VBIOS to select dig matching to link order wise. A significant amount of dal logic makes assumption we are using preferred dig for eDP and if this isn't the case then seamless boot is not supported. Reviewed-by:
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Aurabindo Pillai authored
[Why&How] If the timing generator isnt running, it does not make sense to trigger a sync on the corresponding OTG. Check this condition before starting. Otherwise, this will cause error like: *ERROR* GSL: Timeout on reset trigger! Fixes: dc55b106 ("drm/amd/display: Disable phantom OTG after enable for plane disable") Reviewed-by:
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Chris Park authored
[Why] DTB DTO is programmed more correctly during link enable. Programming them on CLK update which may arrive frequently and sporadically per flip throws off DTB DTO. [How] Remove DTB DTO programming on clock update. Reviewed-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Chris Park <Chris.Park@amd.com> Tested-by:
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- 02 Dec, 2022 8 commits
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Alex Deucher authored
Expand the GPUVM documentation to better describe the hardware functionality and use cases it serves. v2: Fixed a couple of spelling mistakes. Reviewed-by:
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Alex Deucher authored
Add definitions to clarify GPU virtual memory. v2: clarify the terms a bit more Reviewed-by:
Peter Maucher <bellosilicio@gmail.com> Signed-off-by:
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Prike Liang authored
In the SDMA s0ix save process requires to turn off SDMA ring buffer for avoiding the SDMA in-flight request, otherwise will suffer from SDMA page fault which causes by page request from in-flight SDMA ring accessing at SDMA restore phase. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2248 Cc: stable@vger.kernel.org # 6.0,5.15+ Fixes: f8f4e2a5 ("drm/amdgpu: skipping SDMA hw_init and hw_fini for S0ix.") Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Jiadong.Zhu authored
Trigger Mid-Command Buffer Preemption according to the priority of the software rings and the hw fence signalling condition. The muxer saves the locations of the indirect buffer frames from the software ring together with the fence sequence number in its fifo queue, and pops out those records when the fences are signalled. The locations are used to resubmit packages in preemption scenarios by coping the chunks from the software ring. v2: Update comment style. v3: Fix conflict caused by previous modifications. v4: Remove unnecessary prints. v5: Fix corner cases for resubmission cases. v6: Refactor functions for resubmission, calling fence_process in irq handler. v7: Solve conflict for removing amdgpu_sw_ring.c. v8: Add time threshold to judge if preemption request is needed. v9: Correct comment spelling. Set fence emit timestamp before rsu assignment. Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Signed-off-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Jiadong.Zhu authored
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the preemption done. 2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs. v2: Restyle code not to use ternary operator. v3: Modify code format. v4: Enable Mid-Command Buffer Preemption for gfx9 by default. v5: Optimize the flag bit set for emit_fence. v6: Modify log message for preemption timeout. Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Signed-off-by:
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Jiadong.Zhu authored
Set ring functions with software ring callbacks on gfx9. The software ring could be tested by debugfs_test_ib case. v2: Set sw_ring 2 to enable software ring by default. v3: Remove the parameter for software ring enablement. v4: Use amdgpu_ring_init/fini for software rings. v5: Update for code format. Fix conflict. v6: Remove unnecessary checks and enable software ring on gfx9 by default. v7: Use static array for software ring names and priorities. v8: Stop creating software rings if no gfx ring existed. Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Cc: Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Jiadong.Zhu authored
The software ring is created to support priority context while there is only one hardware queue for gfx. Every software ring has its fence driver and could be used as an ordinary ring for the GPU scheduler. Multiple software rings are bound to a real ring with the ring muxer. The packages committed on the software ring are copied to the real ring. v2: Use array to store software ring entry. v3: Remove unnecessary prints. v4: Remove amdgpu_ring_sw_init/fini functions, using gtt for sw ring buffer for later dma copy optimization. v5: Allocate ring entry dynamically in the muxer. v6: Update comments for the ring muxer. v7: Modify for function naming. v8: Combine software ring functions into amdgpu_ring_mux.c v9: Use kernel-doc comment on the get_rptr function. Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Signed-off-by:
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Hamza Mahfooz authored
Currently, userspace doesn't have a way to communicate selective updates to displays. So, enable support for FB_DAMAGE_CLIPS for DCN ASICs newer than DCN301, convert DRM damage clips to dc dirty rectangles and fill them into dirty_rects in fill_dc_dirty_rects(). Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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- 01 Dec, 2022 2 commits
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Peter Maucher authored
The amdgpu kernel module has supported RDNA for a while, mention that in the module description. v2: Add CDNA as well (Alex) Signed-off-by:
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Peter Maucher authored
Document difference between amdgpu.gartsize and amdgpu.gttsize module parameters, as initially explained by Alex Deucher here: https://lists.freedesktop.org/archives/dri-devel/2022-October/375358.html v2: minor cleanups (Alex) Signed-off-by:
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