- 23 Jun, 2023 4 commits
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Palmer Dabbelt authored
Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> Do the various bits needed to drop the additionalProperties: true that we currently have in riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes. * b4-shazam-merge: dt-bindings: riscv: cpus: switch to unevaluatedProperties: false dt-bindings: riscv: cpus: add a ref the common cpu schema Link: https://lore.kernel.org/r/20230615-creamer-emu-ade0fa0bdb68@spudSigned-off-by:
Palmer Dabbelt <palmer@rivosinc.com>
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Song Shuai authored
During hibernation or restoration, freeze_secondary_cpus checks num_online_cpus via BUG_ON, and the subsequent save_processor_state also does the checking with WARN_ON. In the case of CONFIG_PM_SLEEP_SMP=n, freeze_secondary_cpus is not defined, but the sole possible condition to disable CONFIG_PM_SLEEP_SMP is !SMP where num_online_cpus is always 1. We also don't have to check it in save_processor_state. So remove the unnecessary checking in save_processor_state. Fixes: c0317210 ("RISC-V: Add arch functions to support hibernation/suspend-to-disk") Signed-off-by:
Song Shuai <songshuaishuai@tinylab.org> Reviewed-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230609075049.2651723-4-songshuaishuai@tinylab.orgSigned-off-by:
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Palmer Dabbelt authored
guoren@kernel.org <guoren@kernel.org> says: From: Guo Ren <guoren@linux.alibaba.com> This patch series adds independent irq/softirq stacks to decrease the press of the thread stack. Also, add a thread STACK_SIZE config for users to adjust the proper size during compile time. * b4-shazam-merge: riscv: stack: Add config of thread stack size riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACK riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACK Link: https://lore.kernel.org/r/20230614013018.2168426-1-guoren@kernel.orgSigned-off-by:
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Palmer Dabbelt authored
Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> Here are some bits that were discussed with Drew on the "should we allow caps" threads that I have now created patches for: - splitting of riscv_of_processor_hartid() into two distinct functions, one for use purely during early boot, prior to the establishment of the possible-cpus mask & another to fit the other current use-cases - that then allows us to then completely skip some validation of the hartid in the parser - the biggest diff in the series is a rework of the comments in the parser, as I have mostly found the existing (sparse) ones to not be all that helpful whenever I have to go back and look at it - from writing the comments, I found a conditional doing a bit of a dance that I found counter-intuitive, so I've had a go at making that match what I would expect a little better - `i` implies 4 other extensions, so add them as extensions and set them for the craic. Sure why not like... * b4-shazam-merge: RISC-V: always report presence of extensions formerly part of the base ISA dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support RISC-V: remove decrement/increment dance in ISA string parser RISC-V: rework comments in ISA string parser RISC-V: validate riscv,isa at boot, not during ISA string parsing RISC-V: split early & late of_node to hartid mapping RISC-V: simplify register width check in ISA string parsing Link: https://lore.kernel.org/r/20230607-audacity-overhaul-82bb867a825f@spudSigned-off-by:
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- 22 Jun, 2023 5 commits
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Conor Dooley authored
To permit validation of cpu nodes, swap "additionalProperties: true" out for "unevaluatedProperties: false". Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
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Conor Dooley authored
To permit validation of RISC-V cpu nodes, "additionalProperties: true" needs to be swapped for "unevaluatedProperties: false". To facilitate this in a way that passes dt_binding_check, a reference to the cpu schema is required. Disallow the generic cache-op-block-size property that that drags in, since the RISC-V CBO extensions do not require a common size, and have individual properties. Signed-off-by:
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Guo Ren authored
The commit 0cac21b0 ("riscv: use 16KB kernel stack on 64-bit") increases the thread size mandatory, but some scenarios, such as D1 with a small memory footprint, would suffer from that. After independent irq stack support, let's give users a choice to determine their custom stack size. Link: https://lore.kernel.org/linux-riscv/5f6e6c39-b846-4392-b468-02202404de28@www.fastmail.com/Suggested-by:
Arnd Bergmann <arnd@arndb.de> Tested-by:
Jisheng Zhang <jszhang@kernel.org> Signed-off-by:
Guo Ren <guoren@linux.alibaba.com> Signed-off-by:
Guo Ren <guoren@kernel.org> Link: https://lore.kernel.org/r/20230614013018.2168426-4-guoren@kernel.orgSigned-off-by:
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Guo Ren authored
Add the HAVE_SOFTIRQ_ON_OWN_STACK feature for the IRQ_STACKS config, and the irq and softirq use the same irq_stack of percpu. Tested-by:
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Guo Ren authored
Add independent irq stacks for percpu to prevent kernel stack overflows. It is also compatible with VMAP_STACK by arch_alloc_vmap_stack. Tested-by:
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- 21 Jun, 2023 7 commits
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Conor Dooley authored
Of these four extensions, two were part of the base ISA when the port was written and are required by the kernel. The other two are implied when `i` is in riscv,isa on DT systems. There's not much that userspace can do with this extra information, but there is no harm in reporting an ISA string that closer resembles the current versions of the specifications either. Signed-off-by:
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Conor Dooley authored
Similar to commit 41ebfc91 ("dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support"), the Zicntr and Zihpm extensions also used to be part of the base ISA but were removed after the bindings were merged. Document the assumption of their presence in the base ISA. Suggested-by:
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Conor Dooley authored
While expanding on the comments in the ISA string parsing code, I noticed that the conditional decrement of `isa` at the end of the loop was a bit odd. The parsing code expects that at the start of the for loop, `isa` will point to the first character of the next unparsed extension. However, depending on what the next extension is, this may not be true. Unless the next extension is a multi-letter extension preceded by an underscore, `isa` will either point to the string's null-terminator or to the first character of the next extension, once the switch statement has been evaluated. Obviously incrementing `isa` at the end of the loop could cause it to increment past the null terminator or miss a single letter extension, so `isa` is conditionally decremented, just so that the loop can increment it again. It's easier to understand the code if, instead of this decrement + increment dance, we instead use a while loop & rely on the handling of individual extension types to leave `isa` pointing to the first character of the next extension. As already mentioned, this won't be the case where the following extension is multi-letter & preceded by an underscore. To handle that, invert the check and increment rather than decrement. Hopefully this eliminates a "huh?!?" moment the next time somebody tries to understand this code. Reviewed-by:
Andrew Jones <ajones@ventanamicro.com> Signed-off-by:
Sunil V L <sunilvl@ventanamicro.com> Link: https://lore.kernel.org/r/20230607-estate-left-f20faabefb89@spudSigned-off-by:
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Conor Dooley authored
I have found these comments to not be at all helpful whenever I look at the parser. Further, the comments in the default case (single letter parser) are not quite right either. Group the comments into a larger one at the start of each case, that attempts to explain things at a higher level. Reviewed-by:
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Conor Dooley authored
Since riscv_fill_hwcap() now only iterates over possible cpus, the basic validation of whether riscv,isa contains "rv<width>" can be moved to riscv_early_of_processor_hartid(). Further, "ima" support is required by the kernel, so reject any CPU not fitting the bill. Reviewed-by:
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Conor Dooley authored
Some back and forth with Drew [1] about riscv_fill_hwcap() resulted in the realisation that it is not very useful to parse the DT & perform validation of riscv,isa every time we would like to get the id for a hart. Although it is no longer called in riscv_fill_hwcap(), riscv_of_processor_hartid() is called in several other places. Notably in setup_smp() it forms part of the logic for filling the mask of possible CPUs. Since a possible CPU must have passed this basic validation of riscv,isa, a repeat validation is not required. Rename riscv_of_processor_id() to riscv_early_of_processor_id(), which will be called from setup_smp() & introduce a new riscv_of_processor_id() which makes use of the pre-populated mask of possible cpus. Link: https://lore.kernel.org/linux-riscv/xvdswl3iyikwvamny7ikrxo2ncuixshtg3f6uucjahpe3xpc5c@ud4cz4fkg5dj/ [1] Reviewed-by:
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Conor Dooley authored
Saving off the `isa` pointer to a temp variable, followed by checking if it has been incremented is a bit of an odd pattern. Perhaps it was done to avoid a funky looking if statement mixed with the ifdeffery. Now that we use IS_ENABLED() here just return from the parser as soon as we detect a mismatch between the string and the currently running kernel. Reviewed-by:
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- 20 Jun, 2023 5 commits
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Viacheslav Mitrofanov authored
Perf gets the number of supported counters from SBI. If it happens that the number of returned counters more than RISCV_MAX_COUNTERS the code trusts it. It does not lead to an immediate problem but can potentially lead to it. Prevent getting more than RISCV_MAX_COUNTERS from SBI. Signed-off-by:
Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com> Reviewed-by:
Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20230505072058.1049732-1-v.v.mitrofanov@yadro.comSigned-off-by:
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Fangrui Song authored
scall is a deprecated alias for ecall. ecall is used in several places, so there is no assembler compatibility concern. Signed-off-by:
Fangrui Song <maskray@google.com> Link: https://lore.kernel.org/r/20230423223210.126948-1-maskray@google.comSigned-off-by:
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Tiezhu Yang authored
thread.bad_cause is saved in arch_uprobe_pre_xol(), it should be restored in arch_uprobe_{post,abort}_xol() accordingly, otherwise the save operation is meaningless, this change is similar with x86 and powerpc. Signed-off-by:Tiezhu Yang <yangtiezhu@loongson.cn> Acked-by:
Oleg Nesterov <oleg@redhat.com> Reviewed-by:
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Jisheng Zhang authored
Attempt VMA lock-based page fault handling first, and fall back to the existing mmap_lock-based handling if that fails. A simple running the ebizzy benchmark on Lichee Pi 4A shows that PER_VMA_LOCK can improve the ebizzy benchmark by about 32.68%. In theory, the more CPUs, the bigger improvement, but I don't have any HW platform which has more than 4 CPUs. This is the riscv variant of "x86/mm: try VMA lock-based page fault handling first". Signed-off-by:
Suren Baghdasaryan <surenb@google.com> Link: https://lore.kernel.org/r/20230523165942.2630-1-jszhang@kernel.orgSigned-off-by:
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Björn Töpel authored
The RISC-V port requires that kernel PGD entries are to be synchronized between MMs. This is done via the vmalloc_fault() function, that simply copies the PGD entries from init_mm to the faulting one. Historically, faulting in PGD entries have been a source for both bugs [1], and poor performance. One way to get rid of vmalloc faults is by pre-allocating the PGD entries. Pre-allocating the entries potientially wastes 64 * 4K (65 on SV39). The pre-allocation function is pulled from Jörg Rödel's x86 work, with the addition of 3-level page tables (PMD allocations). The pmd_alloc() function needs the ptlock cache to be initialized (when split page locks is enabled), so the pre-allocation is done in a RISC-V specific pgtable_cache_init() implementation. Pre-allocate the kernel PGD entries for the vmalloc/modules area, but only for 64b platforms. Link: https://lore.kernel.org/lkml/20200508144043.13893-1-joro@8bytes.org/ # [1] Signed-off-by:
Björn Töpel <bjorn@rivosinc.com> Reviewed-by:
Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20230531093817.665799-1-bjorn@kernel.orgSigned-off-by:
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- 19 Jun, 2023 9 commits
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Palmer Dabbelt authored
Evan Green <evan@rivosinc.com> says: This change detects the presence of Zba, Zbb, and Zbs extensions and exports them per-hart to userspace via the hwprobe mechanism. Glibc can then use these in setting up hwcaps-based library search paths. There's a little bit of extra housekeeping here: the first change adds Zba and Zbs to the set of extensions the kernel recognizes, and the second change starts tracking ISA features per-hart (in addition to the ANDed mask of features across all harts which the kernel uses to make decisions). Now that we track the ISA information per-hart, we could even fix up /proc/cpuinfo to accurately report extension per-hart, though I've left that out of this series for now. * b4-shazam-merge: RISC-V: hwprobe: Expose Zba, Zbb, and Zbs RISC-V: Track ISA extensions per hart RISC-V: Add Zba, Zbs extension probing Link: https://lore.kernel.org/r/20230509182504.2997252-1-evan@rivosinc.comSigned-off-by:
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Evan Green authored
Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions. These are accurately reported per CPU. Signed-off-by:
Evan Green <evan@rivosinc.com> Reviewed-by:
Heiko Stuebner <heiko.stuebner@vrull.eu> Link: https://lore.kernel.org/r/20230509182504.2997252-4-evan@rivosinc.comSigned-off-by:
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Evan Green authored
The kernel maintains a mask of ISA extensions ANDed together across all harts. Let's also keep a bitmap of ISA extensions for each CPU. Although the kernel is currently unlikely to enable a feature that exists only on some CPUs, we want the ability to report asymmetric CPU extensions accurately to usermode. Note that riscv_fill_hwcaps() runs before the per_cpu_offsets are built, which is why I've used a [NR_CPUS] array rather than per_cpu() data. Signed-off-by:
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Evan Green authored
Add the Zba address bit manipulation extension and Zbs single bit instructions extension into those the kernel is aware of and maintains in its riscv_isa bitmap. Signed-off-by:
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Krzysztof Kozlowski authored
Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Sunil V L authored
Currently the PMU driver is using DT based lookup to find the INTC node for sscofpmf extension. This will not work for ACPI based systems causing the driver to fail to register the PMU overflow interrupt handler. Hence, change the code to use the standard interface to find the INTC node which works irrespective of DT or ACPI. Signed-off-by:
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Sunil V L authored
The arch specific __acpi_map_table can be wrapper around either early_memremap or early_ioremap. But early_memremap routine works with normal pointers whereas __acpi_map_table expects pointers in iomem address space. This causes kernel test bot to fail while using the sparse tool. Fix the issue by using early_ioremap and similar fix done for __acpi_unmap_table. Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202305201427.I7QhPjNW-lkp@intel.com/ Fixes: a91a9ffb ("RISC-V: Add support to build the ACPI core") Signed-off-by:
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Song Shuai authored
The suspend_restore_csrs is called in both __hibernate_cpu_resume and the `else` of subsequent swsusp_arch_suspend. Removing the first call makes both suspend_{save,restore}_csrs left in swsusp_arch_suspend for clean code. Fixes: c0317210 ("RISC-V: Add arch functions to support hibernation/suspend-to-disk") Reviewed-by:JeeHeng Sia <jeeheng.sia@starfivetech.com> Signed-off-by:
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Song Shuai authored
No need to link the x1/ra reg via jalr before suspend_restore_regs So it's better to replace jalr with jr. Signed-off-by:
Song Shuai <suagrfillet@gmail.com> Reviewed-by: JeeHeng Sia <jeeheng.sia@starfivetech.com > Link: https://lore.kernel.org/r/20230519060854.214138-1-suagrfillet@gmail.comSigned-off-by:
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- 14 Jun, 2023 2 commits
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Jisheng Zhang authored
extable relies on the MMU to work properly, so it's useless to include __ex_table sections and build extable related functions for !MMU case. Signed-off-by:
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Ben Dooks authored
If Zicbom is present but there was no riscv,cbom-blocks-size property found during the cpu feeatures probe, or the cbom-block-size is not valid, then the extension will be disabled. Make the print explicitly say this is disabled to ensure that there is no confusion about what is being done. Signed-off-by:
Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by:
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- 08 Jun, 2023 8 commits
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Palmer Dabbelt authored
Andy Chiu <andy.chiu@sifive.com> says: This is the v21 patch series for adding Vector extension support in Linux. Please refer to [1] for the introduction of the patchset. The v21 patch series was aimed to solve build issues from v19, provide usage guideline for the prctl interface, and address review comments on v20. Thank every one who has been reviewing, suggesting on the topic. Hope this get a step closer to the final merge. * b4-shazam-merge: (27 commits) selftests: add .gitignore file for RISC-V hwprobe selftests: Test RISC-V Vector prctl interface riscv: Add documentation for Vector riscv: Enable Vector code to be built riscv: detect assembler support for .option arch riscv: Add sysctl to set the default vector rule for new processes riscv: Add prctl controls for userspace vector management riscv: hwcap: change ELF_HWCAP to a function riscv: KVM: Add vector lazy save/restore support riscv: kvm: Add V extension to KVM ISA riscv: prevent stack corruption by reserving task_pt_regs(p) early riscv: signal: validate altstack to reflect Vector riscv: signal: Report signal frame size to userspace via auxv riscv: signal: Add sigcontext save/restore for vector riscv: signal: check fp-reserved words unconditionally riscv: Add ptrace vector support riscv: Allocate user's vector context in the first-use trap riscv: Add task switch support for vector riscv: Introduce struct/helpers to save/restore per-task Vector state riscv: Introduce riscv_v_vsize to record size of Vector context ... Link: https://lore.kernel.org/r/20230605110724.21391-1-andy.chiu@sifive.comSigned-off-by:
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Andy Chiu authored
The executable file "hwprobe" should be ignored by git, adding it to fix that. Signed-off-by:
Andy Chiu <andy.chiu@sifive.com> Link: https://lore.kernel.org/r/20230605110724.21391-28-andy.chiu@sifive.comSigned-off-by:
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Andy Chiu authored
This add a test for prctl interface that controls the use of userspace Vector. Signed-off-by:
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Andy Chiu authored
This patch add a brief documentation of the userspace interface in regard to the RISC-V Vector extension. Signed-off-by:
Greentime Hu <greentime.hu@sifive.com> Reviewed-by:
Vincent Chen <vincent.chen@sifive.com> Co-developed-by:
Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by:
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Guo Ren authored
This patch adds configs for building Vector code. First it detects the reqired toolchain support for building the code. Then it provides an option setting whether Vector is implicitly enabled to userspace. Signed-off-by:
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Andy Chiu authored
Some extensions use .option arch directive to selectively enable certain extensions in parts of its assembly code. For example, Zbb uses it to inform assmebler to emit bit manipulation instructions. However, supporting of this directive only exist on GNU assembler and has not landed on clang at the moment, making TOOLCHAIN_HAS_ZBB depend on AS_IS_GNU. While it is still under review at https://reviews.llvm.org/D123515, the upcoming Vector patch also requires this feature in assembler. Thus, provide Kconfig AS_HAS_OPTION_ARCH to detect such feature. Then TOOLCHAIN_HAS_XXX will be turned on automatically when the feature land. Suggested-by:
Nathan Chancellor <nathan@kernel.org> Signed-off-by:
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Andy Chiu authored
To support Vector extension, the series exports variable-length vector registers on the signal frame. However, this potentially breaks abi if processing vector registers is required in the signal handler for old binaries. For example, there is such need if user-level context switch is triggerred via signals[1]. For this reason, it is best to leave a decision to distro maintainers, where the enablement of userspace Vector for new launching programs can be controlled. Developers may also need the switch to experiment with. The parameter is configurable through sysctl interface so a distro may turn off Vector early at init script if the break really happens in the wild. The switch will only take effects on new execve() calls once set. This will not effect existing processes that do not call execve(), nor processes which has been set with a non-default vstate_ctrl by making explicit PR_RISCV_V_SET_CONTROL prctl() calls. Link: https://lore.kernel.org/all/87cz4048rp.fsf@all.your.base.are.belong.to.us/Signed-off-by:
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Andy Chiu authored
This patch add two riscv-specific prctls, to allow usespace control the use of vector unit: * PR_RISCV_V_SET_CONTROL: control the permission to use Vector at next, or all following execve for a thread. Turning off a thread's Vector live is not possible since libraries may have registered ifunc that may execute Vector instructions. * PR_RISCV_V_GET_CONTROL: get the same permission setting for the current thread, and the setting for following execve(s). Signed-off-by:
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