- 11 Jun, 2021 7 commits
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Evan Quan authored
As OOB(out-of-band) interface may be used to update the power limits. Thus to make sure the power limits reporting of our driver always reflects the correct values, the internal cache must be aligned carefully. V2: add support for out-of-band of other ASICs align cached current power limit with OOB imposed Signed-off-by:Evan Quan <evan.quan@amd.com> Reviewed-By:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Peng Ju Zhou authored
The original code returns IP version of instantce_0 for every IP. This implementation may be correct for most of IPs. However, for certain IP block (VCN for example), it may have 2 instances and both of them have the same hw_id, BUT they have different revision number (0 and 1). In this case, the original amdgpu_discovery_get_ip_version cannot correct reflects the result and returns false information Signed-off-by:
Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by:
Peng Ju Zhou <PengJu.Zhou@amd.com> Signed-off-by:
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Evan Quan authored
For BACO scenario, PMFW will handle the dpm features disablement and interaction with RLC properly. Driver involvement is unnecessary and error prone. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Evan Quan authored
For some ASICs, the real dpm feature disablement job is handled by PMFW during baco reset and custom pptable loading. Cached dpm feature status need to be updated to pair that. Signed-off-by:
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Evan Quan authored
To correctly kick into BACO state, the audio dev's D-state transition(D0->D3) needs to be PMFW-aware. So, if the audio dev entered D3 state prior to our driver, we need to bring it back to D0 state and make sure there will be a D-state transition on runpm suspend. Signed-off-by:
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Evan Quan authored
Via the fSMC_MSG_ArmD3 message, PMFW can properly act on the Dstate change. Driver involvement for determining the timing for BACO enter/exit is not needed. Signed-off-by:
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Evan Quan authored
As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to be incomplete. Another fix(see link below) has been sent out. Link: https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.quan@amd.com/Signed-off-by:
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- 10 Jun, 2021 21 commits
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Wan Jiabing authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c: 3539:12-42: duplicated argument to && or || ./drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c: 5677:87-123: duplicated argument to && or || Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Wan Jiabing <wanjiabing@vivo.com> Signed-off-by:
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Wan Jiabing authored
Fix the following checkincludes.pl warning: ./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 35 #include "dce110_hw_sequencer.h" 69 #include "dce110_hw_sequencer.h" Reviewed-by: -
Jiapeng Chong authored
Use ARRAY_SIZE instead of dividing sizeof array with sizeof an element. Clean up the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/core/dc_resource.c:448:47-48: WARNING: Use ARRAY_SIZE. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Jiapeng Chong authored
Clean up the following includecheck warning: ./drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c: clk_mgr.h is included more than once. No functional change. Reported-by:
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Graham Sider authored
Perform dependent to independent throttle status translation for aldebaran. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
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Graham Sider authored
Perform dependent to independent throttle status translation for renoir. Signed-off-by:
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Graham Sider authored
Perform dependent to independent throttle status translation for vangogh. Signed-off-by:
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Graham Sider authored
Perform dependent to independent throttle status translation for sienna cichlid. Signed-off-by:
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Graham Sider authored
Perform dependent to independent throttle status translation for navi1x. Signed-off-by:
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Graham Sider authored
Perform dependent to independent throttle status translation for arcturus. Signed-off-by:
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Graham Sider authored
Defines smu_cmn_get_indep_throttler_status which performs ASIC independent translation given a corresponding lookup table. Signed-off-by:
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Graham Sider authored
Add new defines for thermal throttle status bits which are ASIC independent. This bit field will be visible to userspace via gpu_metrics alongside the previous ASIC dependent bit fields. Seperated into four types: power throttlers (16 bits), current throttlers (16 bits), temperature (24 bits), other (8 bits). Signed-off-by:
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Graham Sider authored
This patch set adds support for a new ASIC independant u64 throttler status field (indep_throttle_status). Piggybacks off the gpu_metrics_v1_3 bump and similarly bumps gpu_metrics_v2 version (to v2_2) to add field. Signed-off-by:
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John Clements authored
In the case with xgmi connected to cpu load alternate psp fw Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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John Clements authored
synchronized fw header with latest source Reviewed-by:
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Nirmoy Das authored
Fixes handling when page tables are in system memory. v3: remove struct amdgpu_vm_parser. v2: remove unwanted variable. change amdgpu_amdkfd_validate instead of amdgpu_amdkfd_bo_validate. Signed-off-by:Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Dave Airlie authored
Merge tag 'amd-drm-next-5.14-2021-06-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.14-2021-06-09: amdgpu: - SR-IOV fixes - Smartshift updates - GPUVM TLB flush updates - 16bpc fixed point display fix for DCE11 - BACO cleanups and core refactoring - Aldebaran updates - Initial Yellow Carp support - RAS fixes - PM API cleanup - DC visual confirm updates - DC DP MST fixes - DC DML fixes - Misc code cleanups and bug fixes amdkfd: - Initial Yellow Carp support radeon: - memcpy_to/from_io fixes UAPI: - Add Yellow Carp chip family id Used internally in the kernel driver and by mesa Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210610031649.4006-1-alexander.deucher@amd.com
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
Cross-subsystem Changes: - x86/gpu: add JasperLake to gen11 early quirks (Although the patch lacks the Ack info, it has been Acked by Borislav) Driver Changes: - General DMC improves (Anusha) - More ADL-P enabling (Vandita, Matt, Jose, Mika, Anusha, Imre, Lucas, Jani, Manasi, Ville, Stanislav) - Introduce MBUS relative dbuf offset (Ville) - PSR fixes and improvements (Gwan, Jose, Ville) - Re-enable LTTPR non-transparent LT mode for DPCD_REV < 1.4 (Ville) - Remove duplicated declarations (Shaokun, Wan) - Check HDMI sink deep color capabilities during .mode_valid (Ville) - Fix display flicker screan related to console and FBC (Chris) - Remaining conversions of GRAPHICS_VER (Lucas) - Drop invalid FIXME (Jose) - Fix bigjoiner check in dsc_disable (Vandita) Signed-off-by:
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Dave Airlie authored
This fixes 32-bit arm build due to lack of 64-bit divides. Fixes: cb1c8146 ("drm/ttm: flip the switch for driver allocated resources v2") Link: https://patchwork.freedesktop.org/patch/438442/Reviewed-by:
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Alex Deucher authored
Drop disabling of gfxoff during VCN use. This allows gfxoff to kick in and potentially save power if the user is not using gfx for color space conversion or scaling. VCN1.0 had a bug which prevented it from working properly with gfxoff, so we disabled it while using VCN. That said, most apps today use gfx for scaling and color space conversion rather than overlay planes so it was generally in use anyway. This was fixed on VCN2+, but since we mostly use gfx for color space conversion and scaling and rapidly powering up/down gfx can negate the advantages of gfxoff, we left gfxoff disabled. As more applications use overlay planes for color space conversion and scaling, this starts to be a win, so go ahead and leave gfxoff enabled. Note that VCN1.0 uses vcn_v1_0_idle_work_handler() and vcn_v1_0_ring_begin_use() so they are not affected by this patch. Reviewed-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Boyuan Zhang <Boyuan.Zhang@amd.com> Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 5.14: UAPI Changes: * drm/panfrost: Export AFBC_FEATURES register to userspace Cross-subsystem Changes: * dma-buf: Fix debug printing; Rename dma_resv_*() functions + changes in callers; Cleanups Core Changes: * Add prefetching memcpy for WC * Avoid circular dependency on CONFIG_FB * Cleanups * Documentation fixes throughout DRM * ttm: Make struct ttm_resource the base of all managers + changes in all users of TTM; Add a generic memcpy for page-based iomem; Remove use of VM_MIXEDMAP; Cleanups Driver Changes: * drm/bridge: Add TI SN65DSI83 and SN65DSI84 + DT bindings * drm/hyperv: Add DRM driver for HyperV graphics output * drm/msm: Fix module dependencies * drm/panel: KD53T133: Support rotation * drm/pl111: Fix module dependencies * drm/qxl: Fixes * drm/stm: Cleanups * drm/sun4i: Be explicit about format modifiers * drm/vc4: Use struct gpio_desc; Cleanups * drm/vgem: Cleanups * drm/vmwgfx: Use ttm_bo_move_null() if there's nothing to copy * fbdev/mach64: Cleanups * fbdev/mb862xx: Use DEVICE_ATTR_RO Signed-off-by:
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- 09 Jun, 2021 5 commits
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Stanislav Lisovskiy authored
We currently treat same slice mask as a same DBuf state and skip updating the Dbuf slices, if we detect that. This is wrong as if we have a multi to single pipe change or vice versa, that would be treated as a same Dbuf state and thus no changes required, so we don't get Mbus updated, causing issues. Solution: check also mbus_join, in addition to slices mask. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210527110106.21434-1-stanislav.lisovskiy@intel.com
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Stanislav Lisovskiy authored
CDCLK crawl feature allows to change CDCLK frequency without disabling the actual PLL and doesn't require a full modeset. v2: - Added has_cdclk_crawl as a feature flag to intel_device_info(Matt Roper) - s/gen13_cdclk_pll_crawl/adlp_cdclk_pll_crawl/ (Matt Roper) Cc: Mika Kahola <mika.kahola@intel.com> Reviewed-by:Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
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Vandita Kulkarni authored
This change takes care of resetting the dss_ctl registers in case of dsc_disable, bigjoiner disable and also uncompressed joiner disable. v2: Fix formatting v3: Fix the typo (Mansi) Suggested-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210609065914.4454-1-vandita.kulkarni@intel.com
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Nirmoy Das authored
Use ttm_bo_move_null() instead of ttm_bo_assign_mem(). Signed-off-by:
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Colin Ian King authored
The object surf is not fully initialized and the uninitialized field surf.data is being copied by the call to qxl_bo_create via the call to qxl_gem_object_create. Set surf.data to zero to ensure garbage data from the stack is not being copied. Addresses-Coverity: ("Uninitialized scalar variable") Fixes: f64122c1 ("drm: add new QXL driver. (v1.4)") Signed-off-by:Colin Ian King <colin.king@canonical.com> Link: http://patchwork.freedesktop.org/patch/msgid/20210608161313.161922-1-colin.king@canonical.comSigned-off-by:
Gerd Hoffmann <kraxel@redhat.com>
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- 08 Jun, 2021 7 commits
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Ville Syrjälä authored
AUX logic is often clocked from cdclk. Disable PSR to make sure there are no hw initiated AUX transactions in flight while we change the cdclk frequency. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210608085415.515342-2-gwan-gyeong.mun@intel.com
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Gwan-gyeong Mun authored
This introduces the following function that can exit and activate a psr source when intel_psr is already enabled. - intel_psr_pause(): Pause current PSR. It deactivates current psr state. - intel_psr_resume(): Resume paused PSR. It activates paused psr state. v2: Address Jose's review comment. - Remove unneeded changes around the intel_psr_enable(). - Add intel_psr_post_exit() which processes waiting until PSR is idle and WA for SelectiveFetch. v3: Address Jose's review comment. - Rename intel_psr_post_exit() to intel_psr_wait_exit_locked(). - Move WA_1408330847 to intel_psr_disable_locked() - If the PSR is paused by an explicit intel_psr_paused() call, make the intel_psr_flush() not to activate PSR. v4: Address Jose's review comment. - In order to avoid the scenario of PSR is not active but there is a scheduled psr->work, it changes the check routine of intel_psr_pause() for PSR's enablement from "psr->active" to "psr->enable". Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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Marek Vasut authored
There is not much value in the extra conversion step, the calculations required for the LTDC IP are different than what is used in the drm_display_mode_to_videomode(), so just do the right ones in the LTDC driver right away. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Antonio Borneo <antonio.borneo@foss.st.com> Cc: Benjamin Gaignard <benjamin.gaignard@foss.st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Philippe Cornu <philippe.cornu@foss.st.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Vincent Abriou <vincent.abriou@foss.st.com> Cc: Yannick Fertre <yannick.fertre@foss.st.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com To: dri-devel@lists.freedesktop.org Tested-by:
Yannick Fertré <yannick.fertre@st.com> Signed-off-by:
Philippe Cornu <philippe.cornu@foss.st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210607172457.14471-1-marex@denx.de
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Rohit Khaire authored
This is similar to IH_RB_CNTL programming in navi10_ih_toggle_ring_interrupts Signed-off-by:
Rohit Khaire <rohit.khaire@amd.com> Acked-by:
Horace Chen <horace.chen@amd.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Wyatt Wood authored
Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Po-Ting Chen authored
[Why] To support a new visual confirm mode: swizzle to show the specific color at the screen border according to different surface swizzle mode. Currently we only support the Linear mode with red color. Signed-off-by:
Po-Ting Chen <robin.chen@amd.com> Acked-by:
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