- 01 Sep, 2021 1 commit
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Stephen Boyd authored
- Support video, gpu, display clks on qcom sc7280 SoCs - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs - Multimedia clks (MMCC) on qcom MSM8994/MSM8992 - Migrate to clk_parent_data in gcc-sdm660 - RPMh clks on qcom SM6350 SoCs - Support for Mediatek MT8192 SoCs * clk-qcom: (38 commits) clk: qcom: Add SM6350 GCC driver dt-bindings: clock: Add SM6350 GCC clock bindings clk: qcom: rpmh: Add support for RPMH clocks on SM6350 dt-bindings: clock: Add RPMHCC bindings for SM6350 clk: qcom: adjust selects for SM_VIDEOCC_8150 and SM_VIDEOCC_8250 clk: qcom: Add Global Clock controller (GCC) driver for SM6115 dt-bindings: clk: qcom: gcc-sm6115: Document SM6115 GCC clk: qcom: mmcc-msm8994: Add MSM8992 support clk: qcom: Add msm8994 MMCC driver dt-bindings: clock: Add support for MSM8992/4 MMCC clk: qcom: Add Global Clock Controller driver for MSM8953 dt-bindings: clock: add Qualcomm MSM8953 GCC driver bindings clk: qcom: gcc-sdm660: Replace usage of parent_names clk: qcom: gcc-sdm660: Move parent tables after PLLs clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create PM: runtime: add devm_pm_clk_create helper PM: runtime: add devm_pm_runtime_enable helper clk: qcom: a53-pll: Add MSM8939 a53pll support dt-bindings: clock: Update qcom,a53pll bindings for MSM8939 support clk: qcom: a53pll/mux: Use unique clock name ... * clk-socfpga: clk: socfpga: agilex: add the bypass register for s2f_usr0 clock clk: socfpga: agilex: fix up s2f_user0_clk representation clk: socfpga: agilex: fix the parents of the psi_ref_clk * clk-mediatek: (22 commits) clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167 clk: mediatek: Add MT8192 vencsys clock support clk: mediatek: Add MT8192 vdecsys clock support clk: mediatek: Add MT8192 scp adsp clock support clk: mediatek: Add MT8192 msdc clock support clk: mediatek: Add MT8192 mmsys clock support clk: mediatek: Add MT8192 mfgcfg clock support clk: mediatek: Add MT8192 mdpsys clock support clk: mediatek: Add MT8192 ipesys clock support clk: mediatek: Add MT8192 imp i2c wrapper clock support clk: mediatek: Add MT8192 imgsys clock support clk: mediatek: Add MT8192 camsys clock support clk: mediatek: Add MT8192 audio clock support clk: mediatek: Add MT8192 basic clocks support clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers clk: mediatek: Add configurable enable control to mtk_pll_data clk: mediatek: Fix asymmetrical PLL enable and disable control clk: mediatek: Get regmap without syscon compatible check clk: mediatek: Add dt-bindings of MT8192 clocks dt-bindings: ARM: Mediatek: Add audsys document binding for MT8192 ... * clk-lmk: clk: lmk04832: drop redundant fallthrough statements * clk-x86: clk: x86: Rename clk-lpt to more specific clk-lpss-atom
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- 29 Aug, 2021 7 commits
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Konrad Dybcio authored
This adds Global Clock controller (GCC) driver for SM6350 SoC Acked-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210820203624.232268-3-konrad.dybcio@somainline.orgSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Konrad Dybcio authored
Add device tree bindings for global clock controller on SM6350 SoC. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Konrad Dybcio authored
Add support for RPMH clocks on SM6350 SoCs. Reviewed-by:
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Konrad Dybcio authored
Add bindings and update documentation for clock rpmh driver on SM6350. Reviewed-by:
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Lukas Bulwahn authored
Commit 5658e8cf ("clk: qcom: add video clock controller driver for SM8150") and commit 0e94711a ("clk: qcom: add video clock controller driver for SM8250") add config SM_VIDEOCC_8150 and config SM_VIDEOCC_8250, which select the non-existing configs SDM_GCC_8150 and SDM_GCC_8250, respectively. Hence, ./scripts/checkkconfigsymbols.py warns: SDM_GCC_8150 Referencing files: drivers/clk/qcom/Kconfig SDM_GCC_8250 Referencing files: drivers/clk/qcom/Kconfig It is probably just a typo (or naming confusion of using SM_GCC_xxx and SDM_GCC_xxx for various Qualcomm clock drivers) in the config definitions for config SM_VIDEOCC_8150 and SM_VIDEOCC_8250, and intends to select the existing SM_GCC_8150 and SM_GCC_8250, respectively. Adjust the selects to the existing configs. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20210816135930.11810-1-lukas.bulwahn@gmail.comSigned-off-by:
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Iskren Chernev authored
Add support for the global clock controller found on SM6115 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Based on CAF implementation. GDSCs ported from downstream DT. Signed-off-by:
Iskren Chernev <iskren.chernev@gmail.com> Link: https://lore.kernel.org/r/20210805161107.1194521-3-iskren.chernev@gmail.comSigned-off-by:
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Iskren Chernev authored
Add device tree bindings for global clock controller on SM6115 and SM4250 SoCs (pin and software compatible). Signed-off-by:
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- 26 Aug, 2021 10 commits
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Konrad Dybcio authored
MSM8992 features less clocks & GDSCS and has different freq tables for some of them. Signed-off-by:
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Konrad Dybcio authored
Add a driver for managing MultiMedia SubSystem clocks on msm8994 and its derivatives. Signed-off-by:
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Konrad Dybcio authored
Document the multimedia clock controller found on MSM8992/4. Signed-off-by:
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Vladimir Lypak authored
This driver provides clocks, resets and power domains for MSM8953 and compatible SoCs: APQ8053, SDM450, SDA450, SDM632, SDA632. Signed-off-by:
Vladimir Lypak <junak.pub@gmail.com> Signed-off-by:
Adam Skladowski <a_skl39@protonmail.com> Reviewed-by:
Sireesh Kodali <sireeshkodali@protonmail.com> Link: https://lore.kernel.org/r/IPvVnyRWbHuQFswiFz0W08Kj1dKoH55ddQVyIIPhMJw@cp7-web-043.plabs.chSigned-off-by:
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Vladimir Lypak authored
Add bindings and compatible to document MSM8953 GCC (Global Clock Controller) driver. Signed-off-by:
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Bjorn Andersson authored
Using parent_data and parent_hws, instead of parent_names, does protect against some cases of incompletely defined clock trees. While it turns out that the bug being chased this time was totally unrelated, this patch converts the SDM660 GCC driver to avoid such issues. The "xo" fixed_factor clock is unused within the gcc driver, but referenced from the DSI PHY. So it's left in place until the DSI driver is updated. Tested-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210825204517.1278130-1-bjorn.andersson@linaro.org [sboyd@kernel.org: Reduce diff by moving enum and tables back to original position in previous patch] Signed-off-by:
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Stephen Boyd authored
In the next patch we're going to change these tables to reference the PLL structures directly. Let's move them here so the diff is easier to read. No functional change in this patch. Signed-off-by: -
Dmitry Baryshkov authored
Use two new helpers instead of pm_runtime_enable() and pm_clk_create(), removing the need for calling pm_runtime_disable and pm_clk_destroy(). Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210731195034.979084-4-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
A typical code pattern for pm_clk_create() call is to call it in the _probe function and to call pm_clk_destroy() both from _probe error path and from _remove function. For some drivers the whole remove function would consist of the call to pm_remove_disable(). Add helper function to replace this bolierplate piece of code. Calling devm_pm_clk_create() removes the need for calling pm_clk_destroy() both in the probe()'s error path and in the remove() function. Signed-off-by:
Rafael J. Wysocki <rafael@kernel.org> Signed-off-by:
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Dmitry Baryshkov authored
A typical code pattern for pm_runtime_enable() call is to call it in the _probe function and to call pm_runtime_disable() both from _probe error path and from _remove function. For some drivers the whole remove function would consist of the call to pm_remove_disable(). Add helper function to replace this bolierplate piece of code. Calling devm_pm_runtime_enable() removes the need for calling pm_runtime_disable() both in the probe()'s error path and in the remove() function. Signed-off-by:
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- 06 Aug, 2021 11 commits
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Shawn Guo authored
MSM8939 has 3 a53pll clocks with different frequency table for Cluster0, Cluster1 and CCI. It adds function qcom_a53pll_get_freq_tbl() to create pll_freq_tbl from OPP, so that those a53pll frequencies can be defined in DT with operating-points-v2 bindings rather than being coded in the driver. In this case, one compatible rather than three would be needed for these 3 a53pll clocks. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210704024032.11559-5-shawn.guo@linaro.orgSigned-off-by:
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Shawn Guo authored
Update qcom,a53pll bindings for MSM8939 support: - Add optional operating-points-v2 property - Add MSM8939 specific compatible Signed-off-by:
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Shawn Guo authored
Different from MSM8916 which has only one a53pll/mux clock, MSM8939 gets three for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache Coherent Interconnect). That said, a53pll/mux clock needs to be named uniquely. Append @unit-address of device node to the clock name, so that a53pll/mux will be named like below on MSM8939. a53pll@b016000 a53pll@b116000 a53pll@b1d0000 a53mux@b1d1000 a53mux@b011000 a53mux@b111000 Signed-off-by:
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Shawn Guo authored
The clock source for MSM8916 cpu cores is like below. |\ a53pll --------| \ a53mux +------+ | |------------| cpus | gpll0_vote --------| / +------+ |/ So a53mux rather than a53pll is actually the parent clock of cpu cores. It makes more sense to flag a53mux as critical instead, so that when either a53pll or gpll0_vote is used by cpu cores, the clock will be kept enabled while the other can be disabled. Signed-off-by: -
Bjorn Andersson authored
The GPU clock controller found in SC8180x is a variant of the same block found in SM8150, but with one additional clock frequency for the gmu_clk_src clock. Signed-off-by:
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Konrad Dybcio authored
Add support for RPM-managed clocks on the MDM9607 platform. Signed-off-by:
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Konrad Dybcio authored
Add the dt-binding for the RPM Clock Controller on the MDM9607 SoC. Signed-off-by:
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Vladimir Lypak authored
Add definitions for RPM clocks used on MSM8953 platform. Signed-off-by:
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Vladimir Lypak authored
Add compatible for MSM8953 SoC. Signed-off-by:
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Iskren Chernev authored
Add rpm smd clocks, PMIC and bus clocks which are required on SM4250/6115 for clients to vote on. Signed-off-by:
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Martin Botka authored
Add rpm smd clocks, PMIC and bus clocks which are required on SM6125 for clients to vote on. Signed-off-by:
Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210730215924.733350-2-martin.botka@somainline.orgSigned-off-by:
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- 27 Jul, 2021 11 commits
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Martin Botka authored
Document the newly added compatible for sm6125 rpmcc. Signed-off-by:
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Iskren Chernev authored
Add the dt-binding for the RPM Clock Controller on the SM4250/6115 SoCs. Signed-off-by:
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Andy Shevchenko authored
The LPT stands for Lynxpoint PCH. However the driver is used on a few Intel Atom SoCs. Rename it to reflect this in a way how another clock driver, i.e. clk-pmc-atom, is called. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210722193450.35321-1-andriy.shevchenko@linux.intel.comAcked-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by:
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Liam Beguin authored
When the body of a case statement is empty, it is well understood that it is intentional and explicit fallthrough statements are not required. Drop them. Signed-off-by:
Liam Beguin <liambeguin@gmail.com> Link: https://lore.kernel.org/r/20210708211645.3621902-1-liambeguin@gmail.comSigned-off-by:
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Miles Chen authored
I found that COMMON_CLK_MT8167* do not depend on COMMON_CLK_MT8167, so it is possible to config: CONFIG_COMMON_CLK_MT8167=n CONFIG_COMMON_CLK_MT8167_*=y Although it does not cause build breaks with such configuration, I think it is clearer to make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167. Signed-off-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20210716051732.3422-1-miles.chen@mediatek.comSigned-off-by:
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Bjorn Andersson authored
The clock controller has two additional clock source pairs, in order to support more than a single DisplayPort PHY. List these, so it's possible to describe them all. Also drop the unnecessary freq_tbl for the link clock sources, to allow these parents to be used. Signed-off-by:
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Chun-Jie Chen authored
Add MT8192 vencsys clock provider Signed-off-by:
Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-22-chun-jie.chen@mediatek.comReviewed-by:
Ikjoon Jang <ikjn@chromium.org> Signed-off-by:
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Chun-Jie Chen authored
Add MT8192 vdecsys and vdecsys soc clock providers Signed-off-by:
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Chun-Jie Chen authored
Add MT8192 scp adsp clock provider Signed-off-by:
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Chun-Jie Chen authored
Add MT8192 msdc and msdc top clock providers Signed-off-by:
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Chun-Jie Chen authored
Add MT8192 mmsys clock provider Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20210726105719.15793-18-chun-jie.chen@mediatek.comSigned-off-by:
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