Use the new config symbol ARM_SINGLE_ARMV7M which groups config
symbols used by modern ARMv7-M platforms. This allows supporting
multiple ARMv7-M platforms in one kernel image. However, a common
kernel image requires the combined platforms to share the same
main memory layout to be bootable.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The newly added zx platform causes a build error when
CONFIG_THUMB2_KERNEL is enabled:

arch/arm/mach-zx/headsmp.S:16: Error: invalid immediate for address calculation (value = 0x00000004)

I'm assuming that the ROM code that is calling these entry
points runs in ARM mode, so there would be another problem
in the same file, and we can solve both problems at once
by adding a '.arm' statement that will make zx_resume_jump
and zx_secondary_startup both be built as ARM code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jun Nie <jun.nie@linaro.org>
Tested-by: Jun Nie <jun.nie@linaro.org>

Merge tag 'omap-for-v4.2/omap1-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

Merge fixed up omap1 sparse irq support for v4.2 from Tony Lindgren:

Add support for CONFIG_SPARSE_IRQ for omap1. This takes us a bit closer
to making omap1 support multiarch. After this series we still need to
make omap1 use the common clock framework and fix up the drivers to not
rely on includes from mach and plat directories.

Note that this branch depends on a GPIO driver fix in v4.1-rc3
d2d05c65 ("gpio: omap: Fix regression for MPUIO interrupts").

* tag 'omap-for-v4.2/omap1-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP1: Fix section mismatch warnings for omap_cfg_reg
  ARM: OMAP1: Fix randconfig builds if ARCH_OMAP15XX not selected
  ARM: OMAP1: Change interrupt numbering for sparse IRQ
  ARM: omap1: Switch to use MULTI_IRQ
  ARM: OMAP1: Switch to use generic irqchip in preparation for sparse IRQ
  ARM: OMAP1: Move UART defines to prepare for sparse IRQ

Merge mach-bcm changes from Florian Fainelli:

This pull request contains the following changes:

- Rafal adds an additional fault code to be ignored by the kernel on BCM5301X SoC

- BCM63138 SMP support which:
	* common code to control the PMB bus, to be shared with a reset
	  controller driver in drivers/reset
	* secondary CPU initialization sequence using PMB helpers
	* small changes suggested by Russell King to allow platforms to disable VFP

* tag 'arm-soc/for-4.2/soc-take2' of http://github.com/broadcom/stblinux:
  ARM: BCM63xx: Add SMP support for BCM63138
  ARM: vfp: Add vfp_disable for problematic platforms
  ARM: vfp: Add include guards
  ARM: BCM63xx: Add secondary CPU PMB initialization sequence
  ARM: BCM63xx: Add Broadcom BCM63xx PMB controller helpers
  ARM: BCM5301X: Ignore another (BCM4709 specific) fault code

This is cleary used after init time too for example for
configuring UART wake-up events during runtime. This fixes
section mismatch warnings for randconfig builds that happen
because __init_or_module.
Signed-off-by: Tony Lindgren <tony@atomide.com>

With the omap1 SPARSE_IRQ changes mach/irqs.h is no longer
automatically included. Turns out now we rely on ARCH_OMAP15XX
including hardware.h from memory.h, so without ARCH_OMAP15XX
we get build failures.

As we have legacy drivers still relying on these indirect
includes, let's not add more mach includes to the drivers.
Those have to be removed anyways for multiplatform support.

Let's fix up mach-omap1 to include soc.h where cpu_is_omap
checks are done, and common.h for board-*.c files.

But let's keep the indirect memory.h include for now to avoid
unnecessary churn in the drivers.
Signed-off-by: Tony Lindgren <tony@atomide.com>

Add support for booting the secondary CPU on BCM63138, this involves:

- locating the bootlut to write the reset vector
- powering up the second CPU when we need to using the DT-supplied PMB
  references
- disabling VFP when enabled such that we can keep having SMP
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

Some platforms might not be able to fully utilize VFP when e.g: one CPU
out of two in a SMP complex lacks a VFP unit. Adding code to migrate
task to the CPU which has a VFP unit would be cumbersome and not
performant, instead, just add the ability to disable VFP.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

The sequence to initialize a secondary CPU using the BCM63138 PMB is
extremely specific and represents much more code than any other on-chip
peripheral (AHCI, USB 3.0 or integrated Ethernet switch), as such we
keep that code local and utilize Device Tree to lookup all the resources
we need from the CPU device tree node.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

This patch adds both common register definitions and helper functions
used to issue read/write commands to the Broadcom BCM63xx PMB controller
which is used to power on and release from reset internal on-chip
peripherals such as the integrated Ethernet switch, AHCI, USB, as well
as the secondary CPU core.

This is going to be utilized by the BCM63138 SMP code, as well as by the
BCM63138 reset controller later.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

This patch allows to build the Kernel for Vybrid (VF6xx) SoC
when ARMv7-M CPU is selected. The resulting image runs on the
secondary Cortex-M4 core. This core has equally access to all
peripherals as the main Cortex-A5 core. However, there is no
resource control mechanism, hence when both cores are used
simultaneously, orthogonal device tree's are required.

The boot CPU is dependent on the SoC variant. The available
boards use mostly variants where the Cortex-A5 is the primary
and hence the boot CPU. Booting the secondary Cortex-M4 CPU
needs SoC specific registers written. There is no in kernel
support for this right now, a external userspace utility
called "m4boot" can be used to boot the kernel:

m4boot xipImage initramfs.cpio.lzo vf610m4-colibri.dtb
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This introduces a new top level config symbol ARM_SINGLE_ARMV7M
for non-MMU, ARMv7-M platforms. It also support multiple ARMv7-M
platforms in one kernel image since the cores share the same
basic memory layout and interrupt controller. However, this works
only if the combined platforms also have a similar (main) memory
layout.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Remove the needless differences between MMU/!MMU addruart calls.
This allows to use the same addruart macro on SoC level. Useful
for SoC consisting of multiple CPUs with and without MMU such as
Freescale Vybrid.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

* 'irq/for-arm' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: vf610-mscm: Support NVIC parent chip
  irqchip: nvic: Support hierarchy irq domain
  genirq: generic chip: Support hierarchy domain
  genirq: Add irq_chip_(enable/disable)_parent
  irqdomain: Add non-hierarchy helper irq_domain_set_info

Broadcom ARM devices seem to generate some fault once per boot. We
already have an ignoring handler for BCM4707/BCM4708, but BCM4709
generates different code.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

This pull request for the MAINTAINERS file contains the following changes:

- Brian adds a general "brcmstb" regexp to catch Broadcom Set Top Box related
  changes throughout the Linux tree

* tag 'arm-soc/for-4.2/maintainers' of http://github.com/broadcom/stblinux:
  MAINTAINERS: add brcmstb regex

Change interrupt numbering for sparse IRQ. We do this using
a fixed offset until we can drop irqs.h once all it's users
have been updated.

Note that this depends on the GPIO fix for the MPUIO IRQs
"gpio: omap: Fix regression for MPUIO interrupts".

Also note that this patch adds some extra irq alloc warnings
that will go away when we stop calling irq_alloc_descs
in gpio-omap.c with a follow-up patch.

Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>

This allows us to get a bit further with SPARSE_IRQ and
MULTIARCH support.

Note that we now also rename omap_irq_flags to omap_l2_irq
as that's the omap_irq_flags naming is confusing. It just
contains the interrupt number for the l2 irq.

Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Let's set up things ready for enabling sparse IRQ and remove the
omap_read/write usage.

Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>

These have been indirectly included via asm/irqs.h that
has included mach/hardware.h unless SPARSE_IRQ is specified.
Let's move them to where the other OMAP serial defines for
8250 are.

Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Merge "arm: Xilinx Zynq SoC patches for v4.2" from Michal Simek:

- Change SoC reset path
- Fix SLCR unlock scheme

* tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx:
  ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restart
  ARM: zynq: Use restart_handler mechanism for slcr reset

This makes uniphier behave like all the other platforms that
support TWD, and only select this driver when SMP is enabled.
Without this, we get a compile error on UP builds:

arch/arm/kernel/smp_twd.c: In function 'twd_local_timer_of_register':
arch/arm/kernel/smp_twd.c:391:20: error: 'setup_max_cpus' undeclared (first use in this function)
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Using a dedicated symbol for low-level debugging instead of the
arch symbol will make this platform play nice when enabled on a
kernel that supports multiple platforms.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add a MAINTAINER entry covering all NXP LPC18xx/43xx
machine and drivers files.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Support the NVIC interrupt controller as node parent of the MSCM
interrupt router. On the dual-core variants of Vybird (VF6xx), the
NVIC interrupt controller is used by the Cortex-M4. To support
running Linux on this core too, MSCM needs NVIC parent support too.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-6-git-send-email-stefan@agner.chSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

Add support for hierarchy irq domains. This is required to stack
the MSCM interrupt router and the NVIC controller found in Vybrid
SoC.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-5-git-send-email-stefan@agner.chSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

Use the new helper function irq_domain_set_info to make sure the
function irq_domain_set_hwirq_and_chip is being called, which is
crucial to save irqdomain specific data to irq_data.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-4-git-send-email-stefan@agner.chSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

Add helper irq_chip_enable_parent and irq_chip_disable_parent. The
helper implement the default behavior in case irq_enable or irq_disable
is not implemented for the parent interrupt chip, which is calling the
irq_mask or irq_unmask respectively.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-3-git-send-email-stefan@agner.chSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

This adds the helper irq_domain_set_info() in a non-domain hierarchy
variant. This allows to use the helper for generic chip since not
all chips using generic chip support domain hierarchy.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-2-git-send-email-stefan@agner.chSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

The SLCR is unconditionally unlocked early on boot in zynq_slcr_init()
and not ever re-locked. As such, it is not necessary to explicitly unlock in
the restart codepath.
Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.

Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add a MAINTAINER entry covering all STM32 machine and drivers files.
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add entry for ZTE ARM architecture
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Bring up the secondary core. Enable hotplug with supporting
powering off secondary core.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Use the UART0 peripheral for low level debug. Only the UART port 0 is
currently supported.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add basic code for ZTE ZX296702 platform.

[arnd: removed unused zx296702_init_machine function, and changed
       l2c aux val to default]
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add support for NXP's LPC18xx (Cortex-M3) and LPC43xx (Cortex-M4)
SoCs. These SoCs are NXP's high preformance MCU line and can run at
clock speeds up to 180 MHz for LPC18xx and 204 MHz for LPC43xx.

LPC43xx is more or less a LPC18xx with a Cortex-M4F core and a few
extra peripherals. The LPC43xx series also features one or two
Cortex-M0 cores that can be used to offload the main M4 core.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

STMicrolectronics's STM32 series is a family of Cortex-M
microcontrollers. It is used in various applications, and
proposes a wide range of peripherals.
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge "pxa changes for v4.2 cycle" from Robert Jarzmik:

The main and only feature is the conversion of all pxa variants to clock
framework. This encompasses pxa25x, pxa27x and pxa3xx, for all boards.

This should be a disruptive cycle in the normally quiet pxa history, as
the change can break any platform, and the test were performed on only 4
boards (lubbock, zylonite, mioa701, cm-x300).

* tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux:
  ARM: pxa: Constify irq_domain_ops
  ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk framework
  ARM: pxa: convert eseries to clock framework
  ARM: pxa: Transition pxa25x and pxa27x to clk framework
  ARM: pxa: pxa27x skip default device initialization with DT
  clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc
  ARM: pxa: move gpio11 clock to board files
  ARM: pxa: change clocks init sequence