Set the COMMON_CLK_LAN966X option as a tristate and switch from
builtin_platform_driver() to module_platform_driver() to allow building
and using this driver as a module.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Link: https://lore.kernel.org/r/20220617103306.489466-1-clement.leger@bootlin.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

This driver manages Reset and Clock of STM32MP13 soc.
It uses a clk-stm32-core module to manage stm32 gate, mux and divider
for STM32MP13 and for new future soc.

All gates, muxes, dividers are identify by an index and information
are stored in array (register address, shift, with, flags...)
This is useful when we have two clocks with the same gate or
when one mux manages two output clocks.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Link: https://lore.kernel.org/r/20220516070600.7692-3-gabriel.fernandez@foss.st.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

This driver only registers fixed rate clocks, since the clocks are fully
initialized by the boot loader and should not be changed later, according
to Airoha.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Link: https://lore.kernel.org/r/20220314084409.84394-3-nbd@nbd.nameReviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Add driver for Renesas 9-series PCIe clock generators. This driver
is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C
PCIe clock generators, currently the only tested and supported chip
is 9FGV0241.

The driver is capable of configuring per-chip spread spectrum mode
and output amplitude, as well as per-output slew rate.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20220226040723.143705-3-marex@denx.de
[sboyd@kernel.org: Use non-underscore API for fixed factor]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Signed-off-by: Martin Povišer <povik+lin@cutebit.org>

Link: https://lore.kernel.org/r/20220312135722.20770-1-povik+lin@cutebit.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Add a common clock driver for NCO blocks found on Apple SoCs where they
are typically the generators of audio clocks.
Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
Link: https://lore.kernel.org/r/20220208183411.61090-3-povik+lin@cutebit.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Add support for clock configuration on Microchip PolarFire SoC
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Co-developed-by: Padmarao Begari <padmarao.begari@microchip.com>
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220222121143.3316880-2-conor.dooley@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

The LAN966x Generic Clock Controller is only present on Microchip
LAN966x SoCs.  Hence add a dependency on SOC_LAN966, to prevent asking
the user about this driver when configuring a kernel without LAN966x SoC
support.

Fixes: 54104ee0 ("clk: lan966x: Add lan966x SoC clock driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/eb102eae05e5667b9bd342a0c387f7f262d24bda.1645716471.git.geert+renesas@glider.beReviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Let's test various parts of the rate-related clock API with the kunit
testing framework.

Cc: kunit-dev@googlegroups.com
Tested-by: Daniel Latypov <dlatypov@google.com>
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220225143534.405820-3-maxime@cerno.techSigned-off-by: Stephen Boyd <sboyd@kernel.org>

If the config options HAS_IOMEM is not set then the driver fails to link
with the following error:
clk-lan966x.c:(.text+0x950): undefined reference to
`devm_platform_ioremap_resource'

Therefor add missing dependencies: HAS_IOMEM and OF.

Fixes: 54104ee0 ("clk: lan966x: Add lan966x SoC clock driver")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20220219141536.460812-1-horatiu.vultur@microchip.comReviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Regmap gives us caching, debugging infrastructure and other things for
free and does away with open-coded bit-fiddling implementations.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-10-daniel@zonque.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Test various parts of the clk gate implementation with the kunit testing
framework.
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Acked-by: Daniel Latypov <dlatypov@google.com>
Cc: <kunit-dev@googlegroups.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220120175902.2165958-1-sboyd@kernel.org

Commit 21e74330 ("clk: stm32mp1: new compatible for secure RCC support")
introduced a new Kconfig option COMMON_CLK_STM32MP157_SCMI which is not
used anywhere.

Further, it looks like this Kconfig option is just to select bunch of other
options which doesn't sound correct to me. There is no need for another
SCMI firmware based clock driver and hence the same applies for the config
option too.

Let us just drop the unused COMMON_CLK_STM32MP157_SCMI before it gives
someone idea to write a specific clock driver for this SoC/platform.

Cc: Etienne Carriere <etienne.carriere@foss.st.com>
Cc: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Link: https://lore.kernel.org/r/20211015150043.140793-1-sudeep.holla@arm.comReviewed-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Add support for common interface of the common clock and reset driver
for Toshiba Visconti5 and its SoC, TMPV7708. The PIPLLCT provides the PLL,
and the PISMU provides clock and reset functionality.
Each drivers are provided in this patch.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Link: https://lore.kernel.org/r/20211025031038.4180686-4-nobuhiro1.iwamatsu@toshiba.co.jp
[sboyd@kernel.org: Add bitfield.h include to pll.c]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Add a driver for the StarFive JH7100 clock generator.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>

The TPS68470 PMIC provides Clocks, GPIOs and Regulators. At present in
the kernel the Regulators and Clocks are controlled by an OpRegion
driver designed to work with power control methods defined in ACPI, but
some platforms lack those methods, meaning drivers need to be able to
consume the resources of these chips through the usual frameworks.

This commit adds a driver for the clocks provided by the tps68470,
and is designed to bind to the platform_device registered by the
intel_skl_int3472 module.

This is based on this out of tree driver written by Intel:
https://github.com/intel/linux-intel-lts/blob/4.14/base/drivers/clk/clk-tps68470.c
with various cleanups added.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20211203102857.44539-7-hdegoede@redhat.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

This adds Generic Clock Controller driver for lan966x SoC.

Lan966x clock controller contains 3 PLLs - cpu_clk, ddr_clk
and sys_clk. It generates and supplies clock to various
peripherals within SoC.
Register settings required to provide GCK clocking to a
peripheral is as below:
GCK_SRC_SEL     = Select clock source.
GCK_PRESCALER   = Set divider value.
GCK_ENA         = 1 - Enable GCK clock.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Co-developed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103061935.25677-4-kavyasree.kotagiri@microchip.com

We're moving pistachio to generic MIPS kernel. The clk driver
should be avilable to the generic MIPS kernel.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

This driver depends on SPI. Otherwise compilation fails

  clk-lmk04832.c:(.text+0x1668): undefined reference to `spi_get_device_id'
Reported-by: kernel test robot <lkp@intel.com>
Cc: Liam Beguin <lvb@xiphos.com>
Fixes: 3bc61cfd ("clk: add support for the lmk04832")
Link: https://lore.kernel.org/r/20210629060751.3119453-1-sboyd@kernel.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Platform STM32MP1 can be used in configuration where some clock
resources cannot be accessed by Linux kernel when executing in non-secure
state of the CPU(s).
In such configuration, the RCC clock driver must not register clocks
it cannot access.
They are expected to be registered from another clock driver such
as the SCMI clock driver.
This change uses specific compatible string "st,stm32mp1-rcc-secure"
to specify RCC clock driver configuration where RCC is secure.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Link: https://lore.kernel.org/r/20210617051814.12018-12-gabriel.fernandez@foss.st.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

The only known BD70528 use-cases are such that the PMIC is controlled
from separate MCU which is not running Linux. I am not aware of
any Linux driver users. Furthermore, it seems there is no demand for
this IC. Let's ease the maintenance burden and drop the driver. We can
always add it back if there is sudden need for it.
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Link: https://lore.kernel.org/r/937ed0828486a08e2d00bce2815d491c1c9c49b4.1621937490.git.matti.vaittinen@fi.rohmeurope.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

The LMK04832 is an ultra-high performance clock conditioner with JEDEC
JESD204B support and is also pin compatible with the LMK0482x family of
devices.
Signed-off-by: Liam Beguin <lvb@xiphos.com>
Link: https://lore.kernel.org/r/20210423004057.283926-2-liambeguin@gmail.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

This option is now synonymous with CONFIG_HAVE_CLK, so use
the latter globally. Any out-of-tree platform ports that
still use a private clk_get()/clk_put() implementation should
move to CONFIG_COMMON_CLK.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
    * "50m": 50 MHz.
    * "125m": 125 MHz.
    * "150m": 150 MHz.
    * "250m": 250 MHz.
    * "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210410055059.13518-2-sergio.paracuellos@gmail.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

The Intel's eASIC N5X (ARCH_N5X) architecture shares a lot with Agilex
(ARCH_AGILEX) so it uses the same socfpga_agilex.dtsi, with minor
changes.  Also the clock drivers are the same.

However the clock drivers won't be build without ARCH_AGILEX.  One could
assume that ARCH_N5X simply depends on ARCH_AGILEX but this was not
modeled in Kconfig.  In current stage the ARCH_N5X is simply
unbootable.

Add a separate Kconfig entry for clocks used by both ARCH_N5X and
ARCH_AGILEX so the necessary objects will be built if either of them is
selected.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

Add a clock provider driver for the Canaan Kendryte K210 RISC-V SoC.
This new driver with the compatible string "canaan,k210-clk" implements
support for the full clock structure of the K210 SoC. Since it is
required for the correct operation of the SoC, this driver is
selected by default for compilation when the SOC_CANAAN option is
selected.

With this change, the k210-sysctl driver is turned into a simple
platform driver which enables its power bus clock and triggers
populating its child nodes. The sysctl driver retains the SOC early
initialization code, but the implementation now relies on the new
function k210_clk_early_init() provided by the new clk-k210 driver.

The clock structure implemented and many of the coding ideas for the
driver come from the work by Sean Anderson on the K210 support for the
U-Boot project.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

This adds a basic driver for the MPLL block found in MStar/SigmaStar
ARMv7 SoCs.

Currently this driver is only good for calculating the rates of it's
outputs and the actual configuration must be done before the kernel
boots. Usually this is done even before u-boot starts.

This driver targets the MPLL block found in the MSC313/MSC313E but
there is no documentation this chip so the register descriptions for
the another MStar chip the MST786 were used as they seem to match.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210211052206.2955988-5-daniel@0x0f.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

The xlnx_vcu driver is actually a clock controller driver which provides
clocks that can be used by a driver for the encoder/decoder units. There
is no reason to keep this driver in soc. Move the driver to clk.

NOTE: The register mapping actually contains registers for AXI
performance monitoring, but these are not used by the driver.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-16-m.tretter@pengutronix.deSigned-off-by: Stephen Boyd <sboyd@kernel.org>

The intent is to be able to run this driver to access the IP core in setups
where FPGA board is also connected via a PCIe bus. In such cases the number
of combinations explodes, where the host system can be an x86 with Xilinx
Zynq/ZynqMP/Microblaze board connected via PCIe.
Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.

To accommodate for these cases, this change removes the limitation for this
driver to be compilable only on Zynq/Microblaze architectures.
And adds dependencies on the mechanisms required by the driver to work (OF
and HAS_IOMEM).
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-2-alexandru.ardelean@analog.comAcked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Add support for the FlexSPI clock on Freescale Layerscape SoCs. The
clock is a simple divider based one and is located inside the device
configuration space (DCFG).

This will allow switching the SCK frequencies for the FlexSPI interface
on the LS1028A and the LX2160A.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20201108185113.31377-8-michael@walle.cc
[sboyd@kernel.org: Drop modalias, add module table]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

The Freescale QorIQ clock controller is only present on Freescale E500MC
and Layerscape SoCs.  Add platform dependencies to the CLK_QORIQ config
symbol, to avoid asking the user about it when configuring a kernel
without E500MC or Layerscape support.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Li Yang <leoyang.li@nxp.com>
Link: https://lore.kernel.org/r/20201110154750.3285411-1-geert+renesas@glider.beSigned-off-by: Stephen Boyd <sboyd@kernel.org>

The HSDK PLL driver is only useful when building for an ARC HSDK
platform.
As ARC selects OF, the dependency on OF can just be replaced by a
dependency on ARC_SOC_HSDK.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200807094351.1046-1-geert+renesas@glider.beSigned-off-by: Stephen Boyd <sboyd@kernel.org>

use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
use CONFIG_CLK_RKXX for Rk soc clk driver.
Mark CONFIG_CLK_RK3399 to "tristate",
to support building Rk3399 SoC clock driver as module.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200914022304.23908-1-zhangqing@rock-chips.comSigned-off-by: Heiko Stuebner <heiko@sntech.de>

CONFIG_IOMEM does not exist.  The correct symbol to depend on is
CONFIG_HAS_IOMEM.

Fixes: 1e7468bd ("clk: Specify IOMEM dependency for HSDK pll driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200803084835.21838-1-geert+renesas@glider.beSigned-off-by: Stephen Boyd <sboyd@kernel.org>

The HSDK pll driver uses the devm_ioremap_resource function, but does
not specify a dependency on IOMEM in Kconfig. This causes a build
failure on architectures without IOMEM, for example, UML (notably with
make allyesconfig).

Fix this by making CONFIG_CLK_HSDK depend on CONFIG_IOMEM.
Signed-off-by: David Gow <davidgow@google.com>
Link: https://lore.kernel.org/r/20200630043214.1080961-1-davidgow@google.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

There is no need to select RATIONAL in individual drivers,
since common clock symbol does it already.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200614115140.41262-1-andriy.shevchenko@linux.intel.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Since commit 84af7a61 ("checkpatch: kconfig: prefer 'help' over
'---help---'"), the number of '---help---' has been gradually
decreasing, but there are still more than 2400 instances.

This commit finishes the conversion. While I touched the lines,
I also fixed the indentation.

There are a variety of indentation styles found.

  a) 4 spaces + '---help---'
  b) 7 spaces + '---help---'
  c) 8 spaces + '---help---'
  d) 1 space + 1 tab + '---help---'
  e) 1 tab + '---help---'    (correct indentation)
  f) 1 tab + 1 space + '---help---'
  g) 1 tab + 2 spaces + '---help---'

In order to convert all of them to 1 tab + 'help', I ran the
following commend:

  $ find . -name 'Kconfig*' | xargs sed -i 's/^[[:space:]]*---help---/\thelp/'
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>

Baikal-T1 is supposed to be supplied with a high-frequency external
oscillator. But in order to create signals suitable for each IP-block
embedded into the SoC the oscillator output is primarily connected to
a set of CCU PLLs. There are five of them to create clocks for the MIPS
P5600 cores, an embedded DDR controller, SATA, Ethernet and PCIe domains.
The last three domains though named by the biggest system interfaces in
fact include nearly all of the rest SoC peripherals. Each of the PLLs is
based on True Circuits TSMC CLN28HPM IP-core with an interface wrapper
(so called safe PLL' clocks switcher) to simplify the PLL configuration
procedure.

This driver creates the of-based hardware clocks to use them then in
the corresponding subsystems. In order to simplify the driver code we
split the functionality up into the PLLs clocks operations and hardware
clocks declaration/registration procedures.

Even though the PLLs are based on the same IP-core, they may have some
differences. In particular, some CCU PLLs support the output clock change
without gating them (like CPU or PCIe PLLs), while the others don't, some
CCU PLLs are critical and aren't supposed to be gated. In order to cover
all of these cases the hardware clocks driver is designed with an
info-descriptor pattern. So there are special static descriptors declared
for each PLL, which is then used to create a hardware clock with proper
operations. Additionally debugfs-files are provided for each PLL' field
to make sure the implemented rate-PLLs-dividers calculation algorithm is
correct.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20200526222056.18072-4-Sergey.Semin@baikalelectronics.ru
[sboyd@kernel.org: Silence sparse warning about initializing structs
with NULL vs. integer]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

This is a driver for a block that generates master and bit clocks for
the I2S interface. It's separate from the PMUs that generate clocks for
the peripherals.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200519224151.2074597-14-lkundrak@v3.skSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Clock Generation Unit(CGU) is a new clock controller IP of a forthcoming
Intel network processor SoC named Lightning Mountain(LGM). It provides
programming interfaces to control & configure all CPU & peripheral clocks.
Add common clock framework based clock controller driver for CGU.
Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Link: https://lkml.kernel.org/r/42a4f71847714df482bacffdcd84341a4052800b.1587102634.git.rahul.tanwar@linux.intel.com
[sboyd@kernel.org: Kill init function to alloc and cleanup newline]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>