1. 29 Mar, 2006 32 commits
  2. 28 Mar, 2006 8 commits
    • Linus Torvalds's avatar
      Merge master.kernel.org:/home/rmk/linux-2.6-arm · ca9ba447
      Linus Torvalds authored
      * master.kernel.org:/home/rmk/linux-2.6-arm:
        [ARM] 3388/1: ixp23xx: add core ixp23xx support
        [ARM] 3417/1: add support for logicpd pxa270 card engine
        [ARM] 3387/1: ixp23xx: add defconfig
        [ARM] 3377/2: add support for intel xsc3 core
        [ARM] Move ice-dcc code into misc.c
        [ARM] Fix decompressor serial IO to give CRLF not LFCR
        [ARM] proc-v6: mark page table walks outer-cacheable, shared.  Enable NX.
        [ARM] nommu: trivial patch for arch/arm/lib/Makefile
        [ARM] 3416/1: Update LART site URL
        [ARM] 3415/1: Akita: Add missing EXPORT_SYMBOL
        [ARM] 3414/1: ep93xx: reset ethernet controller before uncompressing
      ca9ba447
    • Linus Torvalds's avatar
      Merge master.kernel.org:/home/rmk/linux-2.6-serial · d4965b3e
      Linus Torvalds authored
      * master.kernel.org:/home/rmk/linux-2.6-serial:
        [SERIAL] Provide Cirrus EP93xx AMBA PL010 serial support.
        [SERIAL] amba-pl010: allow platforms to specify modem control method
        [SERIAL] Remove obsoleted au1x00_uart driver
        [SERIAL] Small time UART configuration fix for AU1100 processor
      d4965b3e
    • Lennert Buytenhek's avatar
      [ARM] 3388/1: ixp23xx: add core ixp23xx support · c4713074
      Lennert Buytenhek authored
      Patch from Lennert Buytenhek
      
      This patch adds support for the Intel ixp23xx series of CPUs.  The
      ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
      interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
      MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
      Switch Fabric unit almost identical to the one on the ixp2400, two
      xscale (8250ish) UARTs and a bunch of other stuff.
      
      This patch adds the core ixp23xx support code, and support for the
      ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
      Espresso platforms.
      Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      c4713074
    • Lennert Buytenhek's avatar
      [ARM] 3417/1: add support for logicpd pxa270 card engine · e9937d4b
      Lennert Buytenhek authored
      Patch from Lennert Buytenhek
      
      Add support for the LogicPD PXA270 Card Engine.
      Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: default avatarNicolas Pitre <nico@cam.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      e9937d4b
    • Lennert Buytenhek's avatar
      [ARM] 3387/1: ixp23xx: add defconfig · fa5ebfcc
      Lennert Buytenhek authored
      Patch from Lennert Buytenhek
      
      Add ixp23xx defconfig.
      Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      fa5ebfcc
    • Lennert Buytenhek's avatar
      [ARM] 3377/2: add support for intel xsc3 core · 23bdf86a
      Lennert Buytenhek authored
      Patch from Lennert Buytenhek
      
      This patch adds support for the new XScale v3 core.  This is an
      ARMv5 ISA core with the following additions:
      
      - L2 cache
      - I/O coherency support (on select chipsets)
      - Low-Locality Reference cache attributes (replaces mini-cache)
      - Supersections (v6 compatible)
      - 36-bit addressing (v6 compatible)
      - Single instruction cache line clean/invalidate
      - LRU cache replacement (vs round-robin)
      
      I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
      cores have separate errata and have to handle things like L2, so it
      is simpler to keep it separate.
      
      L2 cache support is currently a build option because the L2 enable
      bit must be set before we enable the MMU and there is no easy way to
      capture command line parameters at this point.
      
      There are still optimizations that can be done such as using LLR for
      copypage (in theory using the exisiting mini-cache code) but those
      can be addressed down the road.
      Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      23bdf86a
    • Linus Torvalds's avatar
      Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq · 9561b03d
      Linus Torvalds authored
      * master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq:
        [CPUFREQ] cpufreq_conservative: keep ignore_nice_load and freq_step values when reselected
        [CPUFREQ] powernow: remove private for_each_cpu_mask()
        [CPUFREQ] hotplug cpu fix for powernow-k8
        [PATCH] cpufreq_ondemand: add range check
        [PATCH] cpufreq_ondemand: keep ignore_nice_load value when it is reselected
        [PATCH] cpufreq_ondemand: Warn if it cannot run due to too long transition latency
        [PATCH] cpufreq_conservative: alternative initialise approach
        [PATCH] cpufreq_conservative: make for_each_cpu() safe
        [PATCH] cpufreq_conservative: alter default responsiveness
        [PATCH] cpufreq_conservative: aligning of codebase with ondemand
      9561b03d
    • Linus Torvalds's avatar
      Merge branch 'cfq-merge' of git://brick.kernel.dk/data/git/linux-2.6-block · 7baf398f
      Linus Torvalds authored
      * 'cfq-merge' of git://brick.kernel.dk/data/git/linux-2.6-block:
        [BLOCK] cfq-iosched: seek and async performance fixes
        [PATCH] ll_rw_blk: fix 80-col offender in put_io_context()
        [PATCH] cfq-iosched: small cfq_choose_req() optimization
        [PATCH] [BLOCK] cfq-iosched: change cfq io context linking from list to tree
      7baf398f