- 16 Jul, 2018 13 commits
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Harry Wentland authored
Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Steven Chiu <Steven.Chiu@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jun Lei authored
[why] Some DTN tests still failing @ 2% Need to reduce. [how] add instrumentation code to driver so we can get more information from failed runs. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Tony Cheng authored
[Why] We sometime require remapping of FB address space to UMA [How] Move address tracking up a layer before we apply address translation Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Nikola Cornij authored
This allows DM to do any necessary updates before MST discovery starts. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Gloria Li authored
[Why] Testing team wants a way to tell if HDR is on or not [How] Program the overscan color to visually indicate the HDR state of the top-most plane Signed-off-by:
Gloria Li <geling.li@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Krunoslav Kovac authored
[Why] Cursor boosting is done via CNVC_CUR register which is DPP, not HUBP Previous commit was implementing it in HUBP functions, and also breaking diags tests. [How] 1. Undo original commit as well as Eric's diags test fix, almost completely 2. Move programming to DPP and call via new dc_stream function 3. Also removing cur_rom_en from dpp_cursor_attributes and programming as part of normal cursor attributes as it depends on cursor color format Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Vitaly Prosyak authored
Hard-coded luts are needed since complex algorithms are used for color and tone mapping. Add the headers for future use. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Junwei Zhang authored
To check rq pointer before adding entity into it. That avoids NULL pointer access in some case. v2: move the check to caller Suggested-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
This change is to support MESA performace optimization. Modify CS IOCTL to allow its input as command buffer and an array of buffer handles to create a temporay bo list and then destroy it when IOCTL completes. This saves on calling for BO_LIST create and destry IOCTLs in MESA and by this improves performance. v2: Avoid inserting the temp list into idr struct. v3: Remove idr alloation from amdgpu_bo_list_create. Remove useless argument from amdgpu_cs_parser_fini Minor cosmetic stuff. v4: Revert amdgpu_bo_list_destroy back to static Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Eric Huang authored
This reverts commit b87079ec. SMU FW team ask to remove this version specific code. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Acked-by:
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Alex Deucher authored
return a uint32_t rather than an int to properly reflect what the function does. Reviewed-by:
Rex Zhu <rezhu@amd.com> Signed-off-by:
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Alex Deucher authored
Split out the shared smumgr code for vega10 and 12 so we don't have duplicate code for both. Reviewed-by:
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Alex Deucher authored
Commented out. Reviewed-by:
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- 13 Jul, 2018 27 commits
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Alex Deucher authored
Rather than calculating it everytime we rebuild the toc buffer, calculate it once initially and then just copy the cached results to the vram buffer. Acked-by:
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Alex Deucher authored
use the structure member directly. Acked-by:
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Alex Deucher authored
use kaddr directly rather than secondary variable. Acked-by:
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Alex Deucher authored
Rather than using the index variable stored in vram. If the device fails to come back online after a resume cycle, reads from vram will return all 1s which will cause a segfault. Based on a patch from Thomas Martitz <kugel@rockbox.org>. This avoids the segfault, but we still need to sort out why the GPU does not come back online after a resume. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105760Acked-by:
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Alex Deucher authored
Use the PP_STATE_SUPPORT_* rather than AMD_CG_SUPPORT_* when communicating with the SMU. Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
[why] Currently we do not turn off autocal when scaling is in bypass. In case vbios enalbes auto scale and our first mode set is a non-scaled mode we have autocal on causing screen corruption. [how] moves turning autocal off to be first thing done during scaler setup Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Hugo Hu authored
[Why] Prevent unexpected color shows if DalMpVisualConfirm enable. [How] Zero out color configuration data for DalMpVisualConfirm when initiating. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Dmytro Laktyushkin authored
DV updated their dml with an option to use max vstartup, this updates dc dml with the same option Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
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Ken Chalmers authored
[Why] The previous code could allow through attempts to enable more streams than there are timing generators, in designs where the number of pipes is greater than the number of timing generators. [How] Compare the new stream count to the resource pool's timing generator count, instead of its pipe count. Also correct a typo in the error message. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Hersen Wu authored
[Why] when hw team does phy parameters tuning, there is need to force dp link rate or lane count grater than the values from dp receiver to check dp tx. current debufs limit link rate, lane count no more than rx caps. [How] remove force settings less than rx caps check v2: Fix typo in title Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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David Francis authored
Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
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David Francis authored
[Why] Regamma/CTM tests require CRC support [How] The CRC registers that were used in DCE exist under different names in DCN. The code was copied from DCE (in dc/dce110/dce110_timing_generator.c) into DCN, and changed to use the DCN register access helper functions. Signed-off-by:
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Fatemeh Darbehani authored
Signed-off-by:
Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by:
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Yue Hin Lau authored
[WHY] PNP cause bsod regression fix [HOW] Add NULL check Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Mikita Lipski authored
[why] Add a switch statement to translate pp's powerlevel enum to dc powerlevel statement enum [how] Add a translator function Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Charlene Liu authored
[why] "DalEnableHDMI20" set to 0, disallow HDMI YCbCr420 and pixel clock > 340Mhz Default is enabled. Signed-off-by:
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Charlene Liu authored
Signed-off-by:
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Leo (Sunpeng) Li authored
[Why] get_channel_status() can return 0 in returned_bytes, and report a successful operation result. This is because it prunes the first status byte out. This was preventing read_channel_reply() from being called (due to the faulty condition), and consequently preventing the AUX reply status from being set. [How] Fix the conditional so that it accounts for when get_channel_status() returns 0 bytes read. [Fixes] Fixes possible edid read failures during S3 resume, where we are now relying on DRM's DP AUX handling. This was an regression introduced by: Author: Harry Wentland <harry.wentland@amd.com> drm/amd/display: Return aux replies directly to DRM Signed-off-by: -
Leo (Sunpeng) Li authored
[Why] There is no point in keeping the AUX reply value in the raw format as returned from reading the AUX_SW_DATA register. [How] Shift it within read_channel_reply(), where the register is read, before returning it. Signed-off-by:
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Eric Bernstein authored
v2: Remove spurious newline changes Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
[Why] Some monitors mark 4K@60 capable HDMI port only have 300MHz TMDS maximum, but the edid includes 4K@60 mode in cea extension block. [How] To enable 4K@60, need to limit BW by allowing YCbCr420 ONLY mode. Add YCbCr420 only support for monitors that do not fully support HDMI2.0, e.g., ASUS PA328. The YCbCr420 only support applies to DCN, DCE112 or higher. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
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Hersen Wu authored
bug fix: phy test PLTAT is special 80bit test pattern. The 80bit data should be hard coded within driver so that user does not need input the deata. previous driver does not have hard coded 80 bits pattern data for PLTPAT. Other than this PLTPAT, user has to input 80 bits pattern data. In case user input less than 10 bytes data, un-input data byte will be filled by 0x00. Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Signed-off-by:
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