- 27 Jun, 2016 3 commits
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Patrik Jakobsson authored
Load specific firmware versions for the DMC instead of using symbolic links. The currently recommended versions are: SKL 1.26, KBL 1.01 and BXT 1.07. Certain DMC versions need workarounds in the driver which forces us to have a tight dependency between firmware and driver. In order to be able to provide a tested and known working configuration we must lock down on a specific DMC firmware version. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by:
Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Acked-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Mika Kuoppala <mika.kuoppala@intel.com> Acked-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Dave Gordon authored
If a context waiting for VBlank were switched out, switching in the next context and generating a CSB event in the process, then the GuC would have to put the context back in the queue, and then observe the subsequent VBlank interrupt so that it could resubmit the suspended context. However, we always set the CTX_CTRL_INHIBIT_SYN_CTX_SWITCH bit in the RING_CONTEXT_CONTROL register, so this case cannot occur. Furthermore we don't use the GuC's internal scheduler or allow it to auto-resubmit workloads. Consequently, the GuC doesn't need to see VBlanks, and by sending them to it we may be waking it up unnecessarily, which might reduce RC6 residency and increase power consumption. So this patch removes the setting of the GFC_FORWARD_VBLANK field from the code that diverts interrupts towards the GuC. (The code to direct interrupts to the host, OTOH, continues to explicitly set the field to "never send VBlanks to the GuC".) v3: Remove the line of code completely (original set the field to ALWAYS forward, v1 changed it to CONDITIONAL forwarding, v2 explicitly set it to NEVER, v3 just doesn't touch it at all, as we know it's already set to NEVER). Signed-off-by:Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (previous version) Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
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Dave Gordon authored
Gen8 versions of these macros were updated a few months ago (e8ebd8e2 drm/i915: eliminate 'temp' in gen8_for_each macros) originally because at least one iterator could generate an out of bounds access, but also because eliminating the 'temp' parameter generated smaller and faster code. Matthew Auld recently noticed the same problem with the gen6 versions and provided a patch https://lists.freedesktop.org/archives/intel-gfx/2016-June/099334.html but while we're changing these, we might as well make them as much like the gen8 versions as possible, including the style of using "&& (..., true)" rather than ": (..., 1) : 0", and of course eliminating the redundant 'temp'. Furthermore, the "all_pdes" version is only used in one place, so we can improve code efficiency by changing both the macro parameters and the calling code to reduce extra dereferences. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Signed-off-by:
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- 24 Jun, 2016 29 commits
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Chris Wilson authored
The contexts only pin space within the global GTT. Therefore forcing the switch to the perma-pinned kernel context only has an effect when trying to evict from and find room within the global GTT. We can then restrict the switch to only when operating on the default context. This is mostly a no-op as full-ppgtt only exists with execlists at present which skips the context switch anyway. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1466776558-21516-7-git-send-email-chris@chris-wilson.co.uk
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Chris Wilson authored
We only need to force a switch to the kernel context placeholder during eviction. All other uses of i915_gpu_idle() just want to wait until existing work on the GPU is idle. Rename i915_gpu_idle() to i915_gem_wait_for_idle() to avoid any implications about "parking" the context first. v2: Tweak an error message if the wait fails for the ilk vtd w/a Signed-off-by:
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Chris Wilson authored
As the L3 remapping is applied before the next execution, there is no need to wait until all previous uses are idle, the application will not occur any sooner. Signed-off-by:
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Chris Wilson authored
When the GPU is reset or state lost through suspend, every default legacy context needs to reload their state - both the golden render state and the L3 mapping. Only context images explicitly saved to memory (i.e. all execlists and non-default legacy contexts) will retain their state across the reset. v2: Rebase Signed-off-by:
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Chris Wilson authored
The kernel context exists simply as a placeholder and should never be executed with a render context. It does not need the golden render state, as that will always be applied to a user context. By skipping the initialisation we can avoid issues in attempting to program the golden render context when trying to make the hardware idle. v2: Rebase Testcase: igt/drm_module_reload_basic #byt Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95634Signed-off-by:
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Chris Wilson authored
This is so that we have symmetry with intel_lrc.c and avoid a source of if (i915.enable_execlists) layering violation within i915_gem_context.c - that is we move the specific handling of the dev_priv->kernel_context for legacy submission into the legacy submission code. This depends upon the init/fini ordering between contexts and engines already defined by intel_lrc.c, and also exporting the context alignment required for pinning the legacy context. v2: Separate out pin/unpin context funcs for greater symmetry with intel_lrc. One more step towards unifying behaviour between the two classes of engines and towards fixing another bug in i915_switch_context vs requests. Signed-off-by:
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Chris Wilson authored
During suspend (or module unload), if we have never accessed the engine (i.e. userspace never submitted a batch to it), the engine is idle. Then we attempt to idle the engine by forcing it to the default context, which actually means we submit a render batch to setup the golden context state and then wait for it to complete. We can skip this entirely as we know the engine is idle. v2: Drop incorrect comment. References: https://bugs.freedesktop.org/show_bug.cgi?id=95634Signed-off-by:
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Chris Wilson authored
The module init/exit routines are a wrapper around the PCI device init/exit, so move them across. Note that in order to avoid exporting the driver struct, instead of manipulating driver.features inside i915_init we instead opt to simply exit if i915.modeset is disabled. Signed-off-by:
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Chris Wilson authored
To reclaim a bit of space from i915_drv.c, we can move the routines that just hook us into the PCI device tree into i915_pci.c Signed-off-by:
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Frank Binns authored
Stop claiming that UMS support is disabled when it's not actually supported anymore. Signed-off-by:
Frank Binns <frank.binns@imgtec.com> Reviewed-by:
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Chris Wilson authored
Don't emit a driver DRM_ERROR for a user passing in an invalid CRTC id, simply report it is missing back to the user. Signed-off-by:
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Chris Wilson authored
The GETPARAM ioctl writes to a user supplied address. If that address is invalid, it is the user's error and not the driver's, so quietly report EFAULT and don't blame ourselves with a DRM_ERROR. Signed-off-by:
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Chris Wilson authored
i915_dma.c used to contain the DRI1/UMS horror show, but now all that remains are the out-of-place driver level interfaces (such as allocating, initialising and registering the driver). These should be in i915_drv.c alongside similar routines for suspend/resume. Signed-off-by:
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Chris Wilson authored
Baby step, update to_i915() conversion from drm_device to drm_i915_private: text data bss dec hex filename 1108812 23207 416 1132435 114793 i915.ko (before) 1104999 23207 416 1128622 1138ae i915.ko (after) Signed-off-by:
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Chris Wilson authored
drm_connector_register_all() is now automatically called by drm_dev_register(), and so we no longer have to do so ourselves (via intel_modeset_register() after calling drm_dev_register()). Similarly for unregistering. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1466773227-7994-8-git-send-email-chris@chris-wilson.co.uk
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Chris Wilson authored
To complete the transition to manual control of load/unload, we need to take over unloading from i915_pci_remove(). This allows us to correctly order our unregister vs shutdown phases, which currently are inverted due to the midlayer. However, the unload sequence is still invalid as we shutdown the driver with the last reference. Ideally, all we want to do is remove the userspace access on device removal, deferring the cleanup to the drm_dev_release() - breaking the reference cycles is then left as an exercise for the reader. Signed-off-by:
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Chris Wilson authored
Take control over allocating, loading and registering the driver from the DRM midlayer by performing it manually from i915_pci_probe. This allows us to carefully control the order of when we setup the hardware vs when it becomes visible to third parties (including userspace). The current ordering makes the driver visible to userspace first (in order to coordinate with removed DRI1 userspace), but that ordering incurs risk. The risk increases as we strive for more asynchronous loading. One side effect of controlling the allocation is that we can allocate both the drm_device + drm_i915_private in one block, the next step towards subclassing. Unload is still left as before, a mix of midlayer and driver. v2: After drm_dev_init(), we should call drm_dev_unref() so that we call drm_dev_release() and free everything from drm_dev_init(). v3: Fixup missed error code for failing to allocate dev_priv Suggested-by:
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Chris Wilson authored
Currently debugfs files are created before the driver is even loads. This gives the opportunity for userspace to open that interface and poke around before the backing data structures are initialised - with the possibility of oopsing or worse. Move the creation of the debugfs files to our registration phase, where we announce our presence to the world when we are ready, i.e the sequence changes from drm_dev_register() -> drm_minor_register() -> drm_debugfs_init() -> i915_debugfs_init() -> i915_driver_load() to drm_dev_register() -> drm_minor_register() -> drm_debugfs_init() -> i915_driver_load() -> i915_debugfs_register() Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Chris Wilson authored
Defer connector registration from during construction to the driver registration phase. This is important for ordering the action correctly, e.g. not using debugfs before it is ready. Signed-off-by:
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Chris Wilson authored
Currently the backlight is being registered in the load phase (before the display and its objects are registered). Move the backlight registration into the analogous phase by performing it from the connector registration, just after its creation. Signed-off-by:
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Chris Wilson authored
With the introduction of a connector->func for callback from drm_connector_register() we can move all the tasks that we want to do upon registration into that callback. Later, this will allow us to reorder the registration and defer it until after the device is setup and ready for userspace. Signed-off-by:
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Chris Wilson authored
Currently setting up the backlight for a panel is sometimes done together with initialising the panel, and sometimes after the connector is registered. The backlight setup does not depend upon connector registration (i.e. access to sysfs/debugfs and the kobject hierachy) so perform it consistently just after panel initialisation. Note the discrepancy here as destroying the panel is done during connector unregistration... Signed-off-by:
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Tvrtko Ursulin authored
Effectively removes one layer of indirection between the mask of possible engines and the engine constructors. Instead of spelling out in code the mapping of HAS_<engine> to constructors, makes more use of the recently added data driven approach by putting engine constructor vfuncs into the table as well. Effect is fewer lines of source and smaller binary. At the same time simplify the error handling since engine destructors can run on unitialized engines anyway. Similar approach could be done for legacy submission is wanted. v2: Removed ugly BUILD_BUG_ONs in favour of newly introduced ENGINE_MASK and HAS_ENGINE macros. Also removed the forward declarations by shuffling functions around. v3: Warn when logical_rings table does not contain enough data and disable the engines which could not be initialized. (Chris Wilson) v4: Chris Wilson suggested a nicer engine init loop. Signed-off-by: -
Daniel Vetter authored
Backmerge drm-next for the reworked device register/unregistering. Chris Wilson needs that to be able to land his i915 load/unload demidlayering. Signed-off-by:Daniel Vetter <daniel.vetter@intel.com>
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git://git.pengutronix.de/git/pza/linuxDave Airlie authored
MT8173 HDMI support - device tree binding documentation for MT8173 HDMI encoder, CEC, DDC, and PHY - drivers for MT8173 HDMI encoder, CEC (HPD only for now), DDC, and PHY - enable HDMI output via a custom SMCCC call - add ddc-i2c-bus property to HDMI connector device tree binding * tag 'mediatek-drm-2016-06-20' of git://git.pengutronix.de/git/pza/linux: dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation drm/mediatek: enable hdmi output control bit drm/mediatek: Add HDMI support dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
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git://linuxtv.org/pinchartl/mediaDave Airlie authored
some rcar-du fixes. * 'drm/next/du' of git://linuxtv.org/pinchartl/media: drm: rcar-du: error message is not needed for EPROBE_DEFER drm: rcar-du: error message is not needed for drm_vblank_init() rcar-du: add/rename DEFR6 TCON bits
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
- Infrastructure for GVT-g (paravirtualized gpu on gen8+), from Zhi Wang - another attemp at nonblocking atomic plane updates - bugfixes and refactoring for GuC doorbell code (Dave Gordon) - GuC command submission enabled by default, if fw available (Dave Gordon) - more bxt w/a (Arun Siluvery) - bxt phy improvements (Imre Deak) - prep work for stolen objects support (Ankitprasa Sharma & Chris Wilson) - skl/bkl w/a update from Mika Kuoppala - bunch of small improvements and fixes all over, as usual * tag 'drm-intel-next-2016-06-20' of git://anongit.freedesktop.org/drm-intel: (81 commits) drm/i915: Update DRIVER_DATE to 20160620 drm/i915: Introduce GVT context creation API drm/i915: Support LRC context single submission drm/i915: Introduce execlist context status change notification drm/i915: Make addressing mode bits in context descriptor configurable drm/i915: Make ring buffer size of a LRC context configurable drm/i915: gvt: Introduce the basic architecture of GVT-g drm/i915: Fold vGPU active check into inner functions drm/i915: Use offsetof() to calculate the offset of members in PVINFO page drm/i915: Factor out i915_pvinfo.h drm/i915: Serialise presentation with imported dmabufs drm/i915: Use atomic commits for legacy page_flips drm/i915: Move fb_bits updating later in atomic_commit drm/i915: nonblocking commit Reapply "drm/i915: Pass atomic states to fbc update, functions." drm/i915: Roll out the helper nonblock tracking drm/i915: Signal drm events for atomic drm/i915/ilk: Don't disable SSC source if it's in use drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission drm/i915/guc: replace assign_doorbell() with select_doorbell_register() ...
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Dave Airlie authored
Merge tag 'topic/drm-misc-2016-06-22-updated' of git://anongit.freedesktop.org/drm-intel into drm-next Again a pile of things all over - Conversion to rst from docbook from Jani. Looks real pretty, and the source is now actually readable (compared to horrible, horrible docbook xml)! https://01.org/linuxgraphics/gfx-docs/drm/ - device register/unregister rework from Chris, with follow-up work from Benjamin. Allows more drivers to demidlayer load/unload and others to remove a bit of boilerplate. - master/auth related cleanup, with docs - some dma-buf polish, merged by Sumit - small stuff all over (like build fixes from Arnd) Group maintainership seems to slowly take off, with both Thierry and Sumit pushing a few things. No hiccups thus far. * tag 'topic/drm-misc-2016-06-22-updated' of git://anongit.freedesktop.org/drm-intel: (68 commits) drm/vc4: Remove unused connector drm/fb-helper: Reduce READ_ONCE(master) to lockless_dereference drm/sun4i: Remove open-coded drm_connector_register_all() drm/vc4: Remove open-coded drm_connector_register_all() drm/atmel-hlcdc: Remove redundant call to drm_connector_unregister_all() drm: document drm_auth.c drm: Clear up master tracking booleans drm: Extract drm_is_current_master drm: Refactor drop/set master code a bit drm: Lobotomize set_busid nonsense for !pci drivers drm: Nuke SET_UNIQUE ioctl drm: Don't call drm_dev_set_unique from platform drivers drm/vgem: Stop calling drm_drv_set_unique drm: Use dev->name as fallback for dev->unique drm: Clean up drm_crtc.h drm: Move master pointer from drm_minor to drm_device drm: sti: rework init sequence drm: sti: use late_register and early_unregister callbacks drm/amdkfd: Clean up inline handling drm: Add callbacks for late registering ...
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Dave Airlie authored
Add basic support for the sii902x RGB -> HDMI bridge. * tag 'drm-sii902x' of github.com:bbrezillon/linux-at91: drm/bridge: Add sii902x DT bindings doc drm/bridge: Add sii902x driver
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- 22 Jun, 2016 8 commits
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Ville Syrjälä authored
During hibernation the cached DP port register value will be left with whatever value we have there when we create the hibernation image. Currently that means the port (and eDP PLL) will be off in the cached value. However when we resume there is no guarantee that the value in the actual register will match the cached value. If i915 isn't loaded in the kernel that loads the hibernation image, the port may well be on (eg. left on by the BIOS). The encoder state readout does the right thing in this case and updates our encoder state to reflect the actual hardware state. However the post-resume modeset will then use the stale cached port register value in intel_dp_link_down() and potentially confuse the hardware. This was caught by the following assert WARNING: CPU: 3 PID: 5288 at ../drivers/gpu/drm/i915/intel_dp.c:2184 assert_edp_pll+0x99/0xa0 [i915] eDP PLL state assertion failure (expected on, current off) on account of the eDP PLL getting prematurely turned off when shutting down the port, since the DP_PLL_ENABLE bit wasn't set in the cached register value. Presumably I introduced this problem in commit 6fec7662 ("drm/i915: Use intel_dp->DP in eDP PLL setup") as before that we didn't update the cached value after shuttting the port down. That's assuming the port got enabled at least once prior to hibernating. If that didn't happen then the cached value would still have been totally out of sync with reality (eg. first boot w/o eDP on, then hibernate, and then resume with eDP on). So, let's fix this properly and refresh the cached register value from the hardware register during resume. DDI platforms shouldn't use the cached value during port disable at least, so shouldn't have this particular issue. They might still have issues if we skip the initial modeset and then try to retrain the link or something. But untangling this DP vs. DDI mess is a bigger topic, so let's jut punt on DDI for now. Cc: Jani Nikula <jani.nikula@intel.com> Cc: stable@vger.kernel.org Fixes: 6fec7662 ("drm/i915: Use intel_dp->DP in eDP PLL setup") Signed-off-by:
Imre Deak <imre.deak@intel.com>
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Imre Deak authored
The wait for panel status helper will only function correctly if the HW panel timings are programmed correctly. Returning prematurely from this helper may lead to obscure bugs later, so sanity check the HW timing registers. v2: - Check the T8, T9 fields too, we do program them (Ville) CC: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Imre Deak authored
This will be needed by the next patch too so factor it out. No functional change. Signed-off-by:
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Imre Deak authored
No functional change. Signed-off-by:
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Imre Deak authored
The PPS registers are backed by power well #0 and as such may be reset after system or runtime suspend (both implying a possible DC9 transition). Fix this by reusing the VLV/CHV PPS pipe-reassignment logic. The difference on BXT is that the PPS instances are not pipe but port (or more accurately pin) specific, so we only need to care about the lost HW state. As opposed to VLV/CHV the SW state is fixed and initialized during connector init. This also paves the way towards using the actual port->PPS instance mapping based on VBT. This fixes eDP link training errors on BXT after suspend, where we started the link training too early due to an incorrect T3 (panel power on) register value. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96436Signed-off-by:
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Imre Deak authored
Move the early PPS initialization calls next to the rest of PPS initialization steps. This allows us to forgo a duplicated call to intel_dp_init_panel_power_sequencer_registers() on VLV/CHV. This will swap the order of DP AUX registration wrt. PPS initialization. There is an existing race here in case of a user space access via the DPAUX device node after DP AUX registration and before calling intel_dp_init_panel_power_sequencer_registers(), but this change won't make this worse. The fix for this is to separate DP AUX initialization and registration, that's a separate work already underway. The order of MST wrt. PPS init as well as the order of intel_dp_init_panel_power_sequencer_registers() wrt. intel_edp_panel_vdd_sanitize() also swap, which is ok, there are no dependencies between these steps. Suggested by Ville. CC: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Imre Deak authored
The initial DPCD read for eDP detection involves using the PPS, but so far we only initialized the PPS registers after the DPCD read. The reason this was done so far is to preserve a possible LVDS PPS HW setup if LVDS is detected but eDP is not. This is not an issue any more after the previous patch, so we can move the init earlier now. This was caught by CI with the PPS sanity checks in place and the initial eDP DPCD readout waiting for the panel power cycle timeout without the PPS registers being initialized. CC: Ville Syrjälä <ville.syrjala@linux.intel.com> CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Atm on IBX/CPT we attempt to detect if eDP is present even if LVDS was already detected and an encoder for it was registered. This involves trying to read out the eDP DPCD, which in turn needs the same power sequencer that LVDS uses. Poking at the VDD line at an unexpected time may or may not interfere with the LVDS panel, but it's probably safer to prevent this. Registering both an LVDS and an eDP connector would also present a similar problem accessing the shared PPS at any point later in an unexpected way. We also need this to be able fix PPS initialization before its first use in the next patch. For that we want to be sure that PPS is not in use by LVDS. v2: - Split out the PPS init fix to a separate patch. (Chris) - Add comment about eDP init depending on LVDS init. (Chris) - Make the use of the intel_encoder ptr less error prone. v3: - Use IBX/CPT reference instead of the incorrect ILK, add a WARN about this. (Ville) v4: - Use a helper to get the lvds encoder instead of opencoding the same. (Ville) CC: Ville Syrjälä <ville.syrjala@linux.intel.com> CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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