- 13 Aug, 2024 29 commits
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Austin Zheng authored
[Why] DML21 does not allocate DET evenly between pipes. May result in underflow when unlocking the pipes as DET could be overallocated. [How] 1. Unlock pipes that have a decreased amount of DET allocation 2. Wait for the double buffer to be updated. 3. Unlock the remaining pipes. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
Austin Zheng <Austin.Zheng@amd.com> Signed-off-by:
Tom Chung <chiahsuan.chung@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Hung authored
[WHY & HOW] dc->clk_mgr is null checked previously in the same function, indicating it might be null. Passing "dc" to "dc->hwss.apply_idle_power_optimizations", which dereferences null "dc->clk_mgr". (The function pointer resolves to "dcn35_apply_idle_power_optimizations".) This fixes 1 FORWARD_NULL issue reported by Coverity. Reviewed-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
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Relja Vojvodic authored
[Why] Currently the handling for 3DLUT is found in multiple different places, which causes issues when the different functions are not in sync with each other. Frequently bugs occur because the LUT handling is broken up, and what has already been handled isn't kept track of well, which can cause earlier changes to the LUT params to be overridden. [How] Remove DMA LUT handling from DCN401 and refactor legacy LUT handling in one place to make it easier to keep track of what has and needs to be done. Reviewed-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by:
Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] Based on power measurement result, in most cases when display clock is higher than Vmin display clock, lowering display clock using dynamic ODM will improve overall power consumption by 0 to 4 watts even if we can't reach Vmin. [how] Allow vmin optimization applied even if dispclk can't reach Vmin. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Wenjing Liu authored
[why & how] There is a coding error which causes incorrect variables to be assigned in DML21 phase 5. Reviewed-by:
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Srinivasan Shanmugam authored
This commit adds a null check for the 'afb' variable in the amdgpu_dm_update_cursor function. Previously, 'afb' was assumed to be null at line 8388, but was used later in the code without a null check. This could potentially lead to a null pointer dereference. Changes since v1: - Moved the null check for 'afb' to the line where 'afb' is used. (Alex) Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8433 amdgpu_dm_update_cursor() error: we previously assumed 'afb' could be null (see line 8388) Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Co-developed-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Sunil Khatri authored
This reverts commit f3392e66. Reviewed-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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Sunil Khatri authored
This reverts commit 58d28380. Reviewed-by:
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Sunil Khatri authored
This reverts commit cd162ae9. Reviewed-by:
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Jack Xiao authored
Add multiple mes ring instances in mes structure to support multiple mes pipes. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jack Xiao authored
Update mes12 api definition. Signed-off-by:
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Sunil Khatri authored
This reverts commit a46a7bef. Reviewed-by:
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Sunil Khatri authored
Add support of vcn ip dump in the devcoredump for vcn_v5_0. Reviewed-by:
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Alex Deucher authored
Add API for resetting kernel queues. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Add API for resetting kernel queues. Reviewed-by:
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Alex Deucher authored
Add API for resetting kernel queues. Reviewed-by:
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Bas Nieuwenhuizen authored
Missing validation ... Checked libdrm and it clears all the structs, so we should be safe to just check everything. Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Geert Uytterhoeven authored
With -Werror: In function ‘r100_cp_init_microcode’, inlined from ‘r100_cp_init’ at drivers/gpu/drm/radeon/r100.c:1136:7: include/linux/printk.h:465:44: error: ‘%s’ directive argument is null [-Werror=format-overflow=] 465 | #define printk(fmt, ...) printk_index_wrap(_printk, fmt, ##__VA_ARGS__) | ^ include/linux/printk.h:437:17: note: in definition of macro ‘printk_index_wrap’ 437 | _p_func(_fmt, ##__VA_ARGS__); \ | ^~~~~~~ include/linux/printk.h:508:9: note: in expansion of macro ‘printk’ 508 | printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) | ^~~~~~ drivers/gpu/drm/radeon/r100.c:1062:17: note: in expansion of macro ‘pr_err’ 1062 | pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name); | ^~~~~~ Fix this by converting the if/else if/... construct into a proper switch() statement with a default to handle the error case. As a bonus, the generated code is ca. 100 bytes smaller (with gcc 11.4.0 targeting arm32). Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Arnd Bergmann authored
Multiple files in amdgpu call amdgpu_ucode_request() with a fw_name variable that the compiler cannot check for being a valid format string, as seen by enabling the (default-disabled) -Wformat-security option: drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c: In function 'amdgpu_mes_init_microcode': drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c:1517:61: error: format not a string literal and no format arguments [-Werror=format-security] 1517 | r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], fw_name); | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c: In function 'amdgpu_uvd_sw_init': drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c:263:9: error: format not a string literal and no format arguments [-Werror=format-security] 263 | r = amdgpu_ucode_request(adev, &adev->uvd.fw, fw_name); | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c: In function 'amdgpu_vce_sw_init': drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c:161:9: error: format not a string literal and no format arguments [-Werror=format-security] 161 | r = amdgpu_ucode_request(adev, &adev->vce.fw, fw_name); | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c: In function 'amdgpu_umsch_mm_init_microcode': drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c:590:9: error: format not a string literal and no format arguments [-Werror=format-security] 590 | r = amdgpu_ucode_request(adev, &adev->umsch_mm.fw, fw_name); | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c: In function 'amdgpu_cgs_get_firmware_info': drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:417:72: error: format not a string literal and no format arguments [-Werror=format-security] 417 | err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name); | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function 'load_dmcu_fw': drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2221:9: error: format not a string literal and no format arguments [-Werror=format-security] 2221 | r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); | ^ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function 'dm_init_microcode': drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5147:9: error: format not a string literal and no format arguments [-Werror=format-security] 5147 | r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); | ^ Change these all to use a "%s" format with the actual name as an argument, to let the compiler prove this to be correct. Fixes: e5a7d047 ("drm/amd: Use `amdgpu_ucode_*` helpers for CGS") Fixes: 52215e2a ("drm/amd: Use `amdgpu_ucode_*` helpers for VCE") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Tobias Jakobi authored
No functional changes. Signed-off-by:
Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by:
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Tobias Jakobi authored
The struct can be static, as it is only used in this translation unit. Signed-off-by:
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Tobias Jakobi authored
The struct can be static, as it is only used in this translation unit. Signed-off-by:
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Remington Brasga authored
A few define's are listed twice with different, incorrect values. This fix sets them appropriately. Signed-off-by:
Remington Brasga <rbrasga@uci.edu> Signed-off-by:
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Colin Ian King authored
There are a several statements with two following semicolons, replace these with just one semicolon. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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WangYuli authored
The struct assertion is failed because sparse cannot parse `#pragma pack(push, 1)` and `#pragma pack(pop)` correctly. GCC's output is still 1-byte-aligned. No harm to memory layout. The error can be filtered out by sparse-diff, but sometimes multiple lines queezed into one, making the sparse-diff thinks its a new error. I'm trying to aviod this by fixing errors. Link: https://lore.kernel.org/all/20230620045919.492128-1-suhui@nfschina.com/ Link: https://lore.kernel.org/all/93d10611-9fbb-4242-87b8-5860b2606042@suswa.mountain/ Fixes: 1721bc1b ("drm/amdgpu: Update VF2PF interface") Cc: Dan Carpenter <dan.carpenter@linaro.org> Cc: wenlunpeng <wenlunpeng@uniontech.com> Reported-by:
Su Hui <suhui@nfschina.com> Signed-off-by:
WangYuli <wangyuli@uniontech.com> Signed-off-by:
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Alex Deucher authored
This needs to be set as well if the IB uses atomics. Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Alex Deucher authored
This needs to be set as well if the IB uses atomics. Reviewed-by:
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Hamza Mahfooz authored
To be able to get to the lowest power state when suspending systems with DCN3.5+, we must be in IPS before the display hardware is put into D3cold. So, to ensure that the system always reaches the lowest power state while suspending, force systems that support IPS to enter idle optimizations before entering D3cold. Reviewed-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Jack Xiao authored
wait memory room until enough before writing mes packets to avoid ring buffer overflow. v2: squash in sched_hw_submission fix Fixes: de324625 ("drm/amdgpu: cleanup MES11 command submission") Fixes: fffe347e ("drm/amdgpu: cleanup MES12 command submission") Signed-off-by:
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- 06 Aug, 2024 11 commits
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Arunpravin Paneer Selvam authored
We require this flag AMDGPU_GEM_CREATE_GFX12_DCC or any other kernel level GFX12 DCC flag to differentiate the DCC buffers and other pinned display buffers(which has TTM_PL_FLAG_CONTIGUOUS enabled). If we use the TTM_PL_FLAG_CONTIGUOUS flag for DCC buffers, we may over allocate for all the pinned display buffers unnecessarily that leads to memory allocation failure. Signed-off-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Acked-by:
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Tim Huang authored
This resolves the unchecded return value warning reported by Coverity. Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
Jesse Zhang <jesse.zhang@amd.com> Signed-off-by:
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Tim Huang authored
This resolves the unchecded return value warning reported by Coverity. Signed-off-by:
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Tim Huang authored
This resolves the unchecked return value warning reported by Coverity. Signed-off-by:
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Frank Min authored
correct sdma7 max dw into 8 Signed-off-by:
Frank Min <Frank.Min@amd.com> Acked-by:
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Arunpravin Paneer Selvam authored
Add address alignment support to the DCC VRAM buffers. v2: - adjust size based on the max_texture_channel_caches values only for GFX12 DCC buffers. - used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only for DCC buffers. - roundup non power of two DCC buffer adjusted size to nearest power of two number as the buddy allocator does not support non power of two alignments. This applies only to the contiguous DCC buffers. v3:(Alex) - rewrite the max texture channel caches comparison code in an algorithmic way to determine the alignment size. v4:(Alex) - Move the logic from amdgpu_vram_mgr_dcc_alignment() to gmc_v12_0.c and add a new gmc func callback for dcc alignment. If the callback is non-NULL, call it to get the alignment, otherwise, use the default. v5:(Alex) - Set the Alignment to a default value if the callback doesn't exist. - Add the callback to amdgpu_gmc_funcs. v6: - Fix checkpatch warning reported by Intel CI. v7:(Christian) - remove the AMDGPU_GEM_CREATE_GFX12_DCC flag and keep a flag that checks the BO pinning and for a specific hw generation. v8:(Christian) - move this check into gmc_v12_0_get_dcc_alignment. v9: - Fix 32bit build errors Signed-off-by: -
Aric Cyr authored
This version brings along following fixes: - Clean up some files style problems - Program the DET segment when initializing pipes in dcn10_hwseq - Fix overlay with pre-blend color processing - Disable SubVP if Hardware Rotation is Used - Fix few things in DML - Re-enable panel replay feature - Fix null pointer dereference under mst+dsc setup Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
Wayne Lin <wayne.lin@amd.com> Tested-by:
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Dillon Varone authored
[WHY & HOW] When DRR is active with variable refresh rate, add the ability to block DRR clamped P-State strategies (such as SubVP). Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
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Gabe Teeger authored
This reverts commit a1526878 ("drm/amd/display: Avoid overflow assignment in link_dp_cts") Due to regression causing DPMS hang. Reviewed-by:
Gabe Teeger <Gabe.Teeger@amd.com> Signed-off-by:
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Hansen Dsouza authored
[why & how] Add clock source selection control functions based on spec Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Signed-off-by:
Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by:
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Chris Park authored
[Why] Coverity picks up a defect with regards to array underflow. [How] Address coverity issue as recommended. Reviewed-by:
Leo Ma <hanghong.ma@amd.com> Signed-off-by:
Chris Park <chris.park@amd.com> Signed-off-by:
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