1. 08 Nov, 2013 32 commits
    • Damien Lespiau's avatar
      drm/i915/bdw: Broadwell has 3 pipes · 4b30553d
      Damien Lespiau authored
      v2: Rebase (Paulo Zanoni)
      
      v3: Rebase on top of num_pipes having moved to intel_device_info.
      
      Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
      Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v2)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      4b30553d
    • Paulo Zanoni's avatar
      drm/i915/bdw: add IS_BROADWELL macro · 4e8058a2
      Paulo Zanoni authored
      For now it's just equivalent to IS_GEN8, but in the future we might
      want to change that (e.g., on Gen 7 we have IS_VALLEYVIEW,
      IS_IVYBRIDGE and IS_HASWELL).
      Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      4e8058a2
    • Ben Widawsky's avatar
      drm/i915/bdw: BSD init for gen8 also · 780f18c8
      Ben Widawsky authored
      This was an oversight and should have been in a previous series
      somewhere.
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      780f18c8
    • Ben Widawsky's avatar
      drm/i915/bdw: ppgtt info in debugfs · 77df6772
      Ben Widawsky authored
      It's not so much that the information is terribly useful, but rather
      that the gen6/7 information is completely useless.
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      77df6772
    • Ville Syrjälä's avatar
      drm/i915/bdw: Don't muck with gtt_size on Gen8 when PPGTT setup fails · b42218c1
      Ville Syrjälä authored
      v2: Resolve rebase conflicts and switch to gen < 8 color for GenX
      checking.
      
      v3: Rebase on top of the address space refactoring.
      Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      b42218c1
    • Ben Widawsky's avatar
      drm/i915/bdw: Render ring flushing · a5f3d68e
      Ben Widawsky authored
      PIPE_CONTROL added the high address dword. I'm not sure how the
      simulator let me get away with this. I've explicitly left out all the
      workarounds from Gen7 because in the minimal digging that I did, most
      don't seem necessary, and the simulator doesn't complain without them
      
      Note that BLT and BSD ring commands had already been updated previously.
      Just render/pipe_control should have been broken.
      
      v2: Squash in a fixup from Ville to follow the recent IVB PIPE_CONTROL
      updates: "BDW uses the IVB PIPE_CONTROL style for specifying GTT vs.
      PPGTT for the PIPE_CONTROL QW/DW write."
      
      v3: Rebase on top of Chris' cleanup to have an explicit ring->scratch
      buffer object instead of an opaque ring->private where everyone stores
      the same stuff inside.
      Reported-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (for the fixup)
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      a5f3d68e
    • Ben Widawsky's avatar
      drm/i915/bdw: unleash PPGTT · 28cf5415
      Ben Widawsky authored
      v2: Squash in fix from Ben: Set PPGTT batches as necessary
      
      This fixes the regression in the last couple of days when we enabled
      PPGTT.
      
      v3: Squash in fixup to still use GTT for secure batches from Ville:
      
      BDW doesn't have a separate secure vs. non-secure bit in
      MI_BATCH_BUFFER_START. So for secure batches we have to simply
      leave the PPGTT bit unset. Fortunately older generations (except
      HSW) had similar limitations so execbuffer already creates a GTT
      mapping for all secure batches.
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      28cf5415
    • Ben Widawsky's avatar
      drm/i915/bdw: Implement PPGTT enable · 94e409c1
      Ben Widawsky authored
      Legacy PPGTT on GEN8 requires programming 4 PDP registers per ring.
      Since all rings are using the same address space with the current code
      the logic is simply to program all the tables we've setup for the PPGTT.
      
      v2: Turn on PPGTT in GFX_MODE
      
      v3: v2 was the wrong patch
      
      v4: Resolve conflicts due to patch series reordering.
      
      v5: Squash in fixup from Ben: Use LRI to write PDPs
      
      The docs (and simulator seems to back up) suggest that we can only
      program legacy PPGTT PDPs with LRI commands.
      
      v6: Rebase around context differences conflicts.
      
      v7: Use #defines for per ring PDPs. (Damien)
      
      v8: Don't use typede'f private_t.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (up to v3 and v7)
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      94e409c1
    • Ben Widawsky's avatar
      drm/i915/bdw: Implement PPGTT insert · 9df15b49
      Ben Widawsky authored
      GEN8 insertion is very similar to GEN6.
      
      v2: Rebase on top of Imre's for_each_sg_page helpers.
      
      v3: Fixup my conversion (spotted by Ville).
      
      v4: Rebase on top of the address space refactoring.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      9df15b49
    • Ben Widawsky's avatar
      drm/i915/bdw: Implement PPGTT clear range · 459108b8
      Ben Widawsky authored
      GEN8 PPGTT range clearing is very similar to GEN6 if we assume that our
      PDEs are all valid, which they should be.
      
      v2: Rebase on top of the address space refactoring.
      
      v3: Rebase on top of the bool use_scratch addition to the clear_range interface.
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      459108b8
    • Ben Widawsky's avatar
      drm/i915/bdw: Initialize the PDEs · b1fe6673
      Ben Widawsky authored
      The upcoming clear and insert routines will expect that PDEs all point
      to valid Page Directories. Doing that lazily doesn't really buy us
      anything.
      
      The page allocation is done regardless earlier in init so it shouldn't
      hurt set the PDEs.
      
      v2: Squash in patches to implement fixed PDE write function:
      
      - If I had done this in the first place, the bug that's going to be
        fixed in an upcoming patch would have been much easier to find.
      
      - Use WB for PDEs.
      
        The PAT bit is used for page size. 2ME PDEs aren't even supported in
        BDW, so this was completely invalid. The solution is to make our
        PDEs WB+LLC instead of the pervious WB+eLLC. As far as I can guess,
        this change won't matter for performance.
      
        Thanks to Ville for the quick correction when discussing on IRC.
      
      v3: Return the pde type for pde encoding (Damien)
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      b1fe6673
    • Ben Widawsky's avatar
      drm/i915/bdw: PPGTT init & cleanup · 37aca44a
      Ben Widawsky authored
      Aside from the potential size increase of the PPGTT, the primary
      difference from previous hardware is the Page Directories are no longer
      carved out of the Global GTT.
      
      Note that the PDE allocation is done as a 8MB contiguous allocation,
      this needs to be eventually fixed (since driver reloading will be a
      pain otherwise). Also, this will be a no-go for real PPGTT support.
      
      v2: Move vtable initialization
      
      v3: Resolve conflicts due to patch series reordering.
      
      v4: Rebase on top of the address space refactoring of the PPGTT
      support. Drop Imre's r-b tag for v2, too outdated by now.
      
      v5: Free the correct amount of memory, "get_order takes size not a page
      count." (Imre)
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      37aca44a
    • Ben Widawsky's avatar
      drm/i915/bdw: Support BDW caching · fbe5d36e
      Ben Widawsky authored
      BDW caching works differently than the previous generations. Instead of
      having bits in the PTE which directly control how the page is cached,
      the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by
      register 0x40e0. This style of caching is functionally equivalent to how
      it works on HSW and before.
      
      v2: Tiny bikeshed as discussed on internal irc.
      
      v3: Squash in patch from Ville to mirror the x86 PAT setup more like
      in arch/x86/mm/pat.c. Primarily, the 0th index will be WB, and not
      uncached.
      
      v4: Comment for reason to not use a 64b write on the PPAT.
      
      v5: Add a FIXME comment that the caching bits in the PAT registers
      might be wrong due to doc confusion.
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      fbe5d36e
    • Ben Widawsky's avatar
      drm/i915/bdw: Add GTT functions · 94ec8f61
      Ben Widawsky authored
      With the PTE clarifications, the bind and clear functions can now be
      added for gen8.
      
      v2: Use for_each_sg_pages in gen8_ggtt_insert_entries.
      
      v3: Drop dev argument to pte encode functions, upstream lost it. Also
      rebase on top of the scratch page movement.
      
      v4: Rebase on top of the new address space vfuncs.
      
      v5: Add the bool use_scratch argument to clear_range and the bool valid argument
      to the PTE encode function to follow upstream changes.
      
      v6: Add a FIXME(BDW) about the size mismatch of the readback check
      that Jon Bloomfield spotted.
      
      v7: Squash in fixup patch from Ben for the posting read to match the
      64bit ptes and so shut up the WARN.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      94ec8f61
    • Ben Widawsky's avatar
      drm/i915/bdw: Create gen8_gtt_pte_t · d31eb10e
      Ben Widawsky authored
      With gen6 PTE type in place, pave the way for the new gen8 type.
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      d31eb10e
    • Ben Widawsky's avatar
      drm/i915/bdw: Make gen8_gmch_probe · 63340133
      Ben Widawsky authored
      Probing gen8 is similar to gen6. To make the code cleaner and more
      maintainable however we can use the probe functions to split it out.
      
      v2: Rebased on top of update gtt probe infrastructure.
      
      v3: Rebased on top of Kenneth' Graunke's ->pte_encode refactoring.
      
      V4: Resolve conflicts with Ben's latest ppgtt patches, also switch to
      gen < 8 testing instead of gen <= 7.
      
      v5: Resolve conflicts with address space vfunc changes in upstream.
      
      v6: Use 39b DMA mask. At least, for this mode, it is the correct mask.
      (Imre)
      
      Cc: Imre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      63340133
    • Ben Widawsky's avatar
    • Ben Widawsky's avatar
      drm/i915/bdw: debugfs updates · 9d3203e1
      Ben Widawsky authored
      All the gen8 debugfs stuff I wasn't too lazy to update. We'll need more
      later, I am certain.
      
      v2: Fix up the register name in the debugfs output as suggested by
      Paulo.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Reviewed-by: default avatarPaulo Zanoni <przanoni@gmail.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      9d3203e1
    • Ben Widawsky's avatar
      drm/i915/bdw: Update MI_FLUSH_DW · 075b3bba
      Ben Widawsky authored
      The code is more verbose than necessary for the reader's sake, hopefully
      the compiler optimizes away the if.
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      075b3bba
    • Ben Widawsky's avatar
      drm/i915/bdw: dispatch updates (64b related) · 1c7a0623
      Ben Widawsky authored
      The command to emit batch buffers has changed to address 48b addresses.
      It seemed reasonable that we could still use the old instruction where
      emitting 0 for length would do the right thing, but it seems to bother
      the simulator when the code does that.
      
      Now the second dword in the command has the upper 16b of the address of
      the batchbuffer.
      
      v2: Remove duplicated vfun assignment.
      
      v3: Squash in VECS support changes from Zhao Yakui <yakui.zhao@intel.com>
      
      v4: Make checkpatch happy.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v2)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      1c7a0623
    • Ben Widawsky's avatar
      drm/i915/bdw: Support 64b relocations · 3c94ceee
      Ben Widawsky authored
      We don't actually return any to userspace yet, however we can pretend
      like we do now so userspace will support it when it happens.
      
      This is just to please Chris as the code itself isn't ready for > 64b
      relocations.
      
      v2: Rebase on top of the refactored relocate_entry_gtt|cpu functions.
      
      v3: Squash in fixup from Rafal Barbalho for 64 byte relocs using cpu
      relocs and those crossing a page boundary.
      
      v4: Squash in a fixup for the fixup from Rafael.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Signed-off-by: default avatarBarbalho, Rafael <rafael.barbalho@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      3c94ceee
    • Ben Widawsky's avatar
      drm/i915/bdw: Add interrupt info to debugfs · a123f157
      Ben Widawsky authored
      v2: Add missed ring interrupt info
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      a123f157
    • Ben Widawsky's avatar
      drm/i915/bdw: Implement interrupt changes · abd58f01
      Ben Widawsky authored
      The interrupt handling implementation remains the same as previous
      generations with the 4 types of registers, status, identity, mask, and
      enable. However the layout of where the bits go have changed entirely.
      To address these changes, all of the interrupt vfuncs needed special
      gen8 code.
      
      The way it works is there is a top level status register now which
      informs the interrupt service routine which unit caused the interrupt,
      and therefore which interrupt registers to read to process the
      interrupt. For display the division is quite logical, a set of interrupt
      registers for each pipe, and in addition to those, a set each for "misc"
      and port.
      
      For GT the things get a bit hairy, as seen by the code. Each of the GT
      units has it's own bits defined. They all look *very similar* and
      resides in 16 bits of a GT register. As an example, RCS and BCS share
      register 0. To compact the code a bit, at a slight expense to
      complexity, this is exactly how the code works as well. 2 structures are
      added to the ring buffer so that our ring buffer interrupt handling code
      knows which ring shares the interrupt registers, and a shift value (ie.
      the top or bottom 16 bits of the register).
      
      The above allows us to kept the interrupt register caching scheme, the
      per interrupt enables, and the code to mask and unmask interrupts
      relatively clean (again at the cost of some more complexity).
      
      Most of the GT units mentioned above are command streamers, and so the
      symmetry should work quite well for even the yet to be implemented rings
      which Broadwell adds.
      
      v2: Fixes up a couple of bugs, and is more verbose about errors in the
      Broadwell interrupt handler.
      
      v3: fix DE_MISC IER offset
      
      v4: Simplify interrupts:
      I totally misread the docs the first time I implemented interrupts, and
      so this should greatly simplify the mess. Unlike GEN6, we never touch
      the regular mask registers in irq_get/put.
      
      v5: Rebased on to of recent pch hotplug setup changes.
      
      v6: Fixup on top of moving num_pipes to intel_info.
      
      v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
      wired up ibx_hpd_irq_setup for gen8.
      
      v8: Rebase on top of Jani's asle handling rework.
      
      v9: Rebase on top of Ben's VECS enabling for Haswell, where he
      unfortunately went OCD on the gt irq #defines. Not that they're still
      not yet fully consistent:
      - Used the GT_RENDER_ #defines + bdw shifts.
      - Dropped the shift from the L3_PARITY stuff, seemed clearer.
      - s/irq_refcount/irq_refcount.gt/
      
      v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
      refactoring from Zhao Yakui <yakui.zhao@intel.com>
      
      v11: Rebase on top of the interrupt cleanups in upstream.
      
      v12: Rebase on top of Ben's DPF changes in upstream.
      
      v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
      exactly needs to be done. Requested by Ben.
      
      v14: Fix the patch.
      - Drop the mask of reserved bits and assorted logic, it doesn't match
        the spec.
      - Do the posting read inconditionally instead of commenting it out.
      - Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
      - Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
        we actually will need to use them.
      - Enclose macros in do {} while (0) (checkpatch).
      - Clear DE_MISC interrupt bits only after having processed them.
      - Fix whitespace fail (checkpatch).
      - Fix overtly long lines where appropriate (checkpatch).
      - Don't use typedef'ed private_t (maintainer-scripts).
      - Align the function parameter list correctly.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      
      bikeshed
      abd58f01
    • Ben Widawsky's avatar
      drm/i915/bdw: support GMS and GGMS changes · 9459d252
      Ben Widawsky authored
      All the BARs have the ability to grow.
      
      v2: Pulled out the simulator workaround to a separate patch.
      Rebased.
      
      v3: Rebase onto latest vlv patches from Jesse.
      
      v4: Rebased on top of the early stolen quirk patch from Jesse.
      
      v5: Use the new macro names.
      s/INTEL_BDW_PCI_IDS_D/INTEL_BDW_D_IDS
      s/INTEL_BDW_PCI_IDS_M/INTEL_BDW_M_IDS
      It's Jesse's fault for not following the convention I originally set.
      
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      9459d252
    • Ben Widawsky's avatar
      drm/i915/bdw: display stuff · 4e0bbc31
      Ben Widawsky authored
      Just enough to make the code not barf...
      
      Init BDW display to look like HSW. For the simulator this should be
      fine, but this will probably require more work.
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      [danvet: Add a FIXME comment about RCS flips being untested on bdw.
      Also add a note that hblank events are reserved on bdw+ in DERRMR.]
      Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      4e0bbc31
    • Ben Widawsky's avatar
      drm/i915/bdw: Clock gating init · 1020a5c2
      Ben Widawsky authored
      Clock gating init is really a catch all function for registers we need
      to write early in loading the driver.
      
      Atm just the bare metal stuff we need, more will surely come.
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      1020a5c2
    • Ben Widawsky's avatar
      drm/i915/bdw: HW context support · 8897644a
      Ben Widawsky authored
      BDW context sizes varies a bit.
      
      v2: Squash in fixup for the hw context size from Ben.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      8897644a
    • Ben Widawsky's avatar
      31a5336e
    • Ben Widawsky's avatar
    • Ben Widawsky's avatar
      drm/i915/bdw: Add device IDs · 4d4dead6
      Ben Widawsky authored
      v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
      suggested by Damien.
      
      v3: Squash in VEBOX enabling from  Zhao Yakui <yakui.zhao@intel.com>
      
      v4: Rebase on top of Jesse's patch to extract all pci ids to
      include/drm/i915_pciids.h.
      
      v4: Replace Halo by its marketing moniker Iris. Requested by Ben.
      
      v5: Switch from info->has*ring to info->ring_mask.
      
      v6: Add 0x16X2 variant (which is newer than this patch)
      Rename to use new naming scheme (Chris)
      Remove Simulator PCI ids. These snuck in during rebase (Chris)
      
      v7: Fix poor sed job from v6
      Make the desktop variants use the desktop macro (Rebase error). Notice
      that this makes no functional difference - it's just confusing.
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      4d4dead6
    • Daniel Vetter's avatar
      drm/i915/bdw: Disable PPGTT for now · 8fe6bd23
      Daniel Vetter authored
      This will be changed once the gen8 code is fully implemented.
      
      v2: Use ENOSYS instead of ENXIO as suggested by Chris.
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      8fe6bd23
    • Ben Widawsky's avatar
      drm/i915/bdw: Initialize BDW forcewake vfuncs · 43d1b647
      Ben Widawsky authored
      Somehow this got missed or dropped during development. The simulator
      does not use forcewake, so it's entirely possible it never worked
      correctly. After the mmio rework, this will end up in an OOPs, and the
      system will not boot.
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      [danvet: Use IS_GEN8 instead of IS_BROADWELL.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      43d1b647
  2. 07 Nov, 2013 1 commit
    • Ben Widawsky's avatar
      drm/i915/bdw: Handle forcewake for writes on gen8 · ab2aa47e
      Ben Widawsky authored
      GEN8 removes the GT FIFO which we've all come to know and love. Instead
      it offers a wider range of optimized registers which always keep a
      shadowed copy, and are fed to the GPU when it wakes.
      
      How this is implemented in hardware is still somewhat of a mystery. As
      far as I can tell, the basic design is as follows:
      
      If the register is not optimized, you must use the old forcewake
      mechanism to bring the GT out of sleep. [1]
      
      If register is in the optimized list the write will signal that the
      GT should begin to come out of whatever sleep state it is in.
      
      While the GT is coming out of sleep, the requested write will be stored
      in an intermediate shadow register.
      
      Do to the fact that the implementation details are not clear, I see
      several risks:
      1. Order is not preserved as it is with GT FIFO. If we issue multiple
      writes to optimized registers, where order matters, we may need to
      serialize it with forcewake.
      2. The optimized registers have only 1 shadowed slot, meaning if we
      issue multiple writes to the same register, and those values need to
      reach the GPU in order, forcewake will be required.
      
      [1] We could implement a SW queue the way the GT FIFO used to work if
      desired.
      
      NOTE: Compile tested only until we get real silicon.
      
      v2:
      - Use a default case to make future platforms also work.
      - Get rid of IS_BROADWELL since that's not yet defined, but we want to
        MMIO as soon as possible.
      
      v3: Apply suggestions from Mika's review:
      - s/optimized/shadowed/
      - invert the logic of the helper so that it does what it says (the
        code itself was correct, just confusing to read).
      
      v4:
      - Squash in lost break.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      ab2aa47e
  3. 05 Nov, 2013 1 commit
  4. 04 Nov, 2013 1 commit
    • Daniel Vetter's avatar
      Merge tag 'v3.12' into drm-intel-next · 7f16e5c1
      Daniel Vetter authored
      I want to merge in the new Broadwell support as a late hw enabling
      pull request. But since the internal branch was based upon our
      drm-intel-nightly integration branch I need to resolve all the
      oustanding conflicts in drm/i915 with a backmerge to make the 60+
      patches apply properly.
      
      We'll propably have some fun because Linus will come up with a
      slightly different merge solution.
      
      Conflicts:
      	drivers/gpu/drm/i915/i915_dma.c
      	drivers/gpu/drm/i915/i915_drv.c
      	drivers/gpu/drm/i915/intel_crt.c
      	drivers/gpu/drm/i915/intel_ddi.c
      	drivers/gpu/drm/i915/intel_display.c
      	drivers/gpu/drm/i915/intel_dp.c
      	drivers/gpu/drm/i915/intel_drv.h
      
      All rather simple adjacent lines changed or partial backports from
      -next to -fixes, with the exception of the thaw code in i915_dma.c.
      That one needed a bit of shuffling to restore the intent.
      
      Oh and the massive header file reordering in intel_drv.h is a bit
      trouble. But not much.
      
      v2: Also don't forget the fixup for the silent conflict that results
      in compile fail ...
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      7f16e5c1
  5. 03 Nov, 2013 3 commits
  6. 02 Nov, 2013 2 commits