For now, let's disable IDLE and STANDBY transitions
until we have a real HW to validate against.
Signed-off-by: Felipe Balbi <balbi@ti.com>

This flag will tell us which direction we're
expecting on the next (data or status) phase.

It will help us catching errors of host going
crazy and requesting data of the wrong direction.
Signed-off-by: Felipe Balbi <balbi@ti.com>

if we don't, the list will be busy forever.
Signed-off-by: Felipe Balbi <balbi@ti.com>

if req->dma isn't DMA_ADDR_INVALID it means gadget driver
mapped the request or allocated from coherent, so it's
unnecessary to do anything.
Signed-off-by: Felipe Balbi <balbi@ti.com>

ensure a few bits are cleared before enabling
what we need.
Signed-off-by: Felipe Balbi <balbi@ti.com>

We must ensure that those bits aren't set as
they should only be used in simulation.
Signed-off-by: Felipe Balbi <balbi@ti.com>

that should be 1 << 16, not 16. Caused so many
problems and we never caught it before.
Signed-off-by: Felipe Balbi <balbi@ti.com>

If the gadget drivers sends a ZLP we are trying to map this this request
which does not work on all implementations. So we simply skip mapping
it.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>

In order to ACK the IRQ we must write back
to the same register the bits we read.
Signed-off-by: Felipe Balbi <balbi@ti.com>

dwc3-wrapper can be used by any other wrapper,
using dwc3-omap makes it clear that we're running
on OMAP SoC.
Signed-off-by: Felipe Balbi <balbi@ti.com>

We need that header because of THIS_MODULE.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>

The OMAP wrapper allows us to either control internal
OTG signals via SW or HW. Different boards might wish
to use one or the other mode of operation. Let's have
have that information passed via platform_data for now.

After DT conversion is finished for OMAP, we can easily
convert this to a DT attribute.
Signed-off-by: Felipe Balbi <balbi@ti.com>

We need to have actual HW in order to implement
and test that part of the code anyway. Until then
it's best to remove it.
Signed-off-by: Felipe Balbi <balbi@ti.com>

trivial patch, no functional changes.
Signed-off-by: Felipe Balbi <balbi@ti.com>

Otherwise that IRQ will trigger forever. It's quite
unnecessary.
Signed-off-by: Felipe Balbi <balbi@ti.com>

dev_dbg() macro expects a device pointer as
argument, not a memory base address.
Signed-off-by: Felipe Balbi <balbi@ti.com>

Start tracking the next expected event and act
on the error conditions as suggested by databook.
Signed-off-by: Felipe Balbi <balbi@ti.com>

this field will hold the next expected event.

In certain cases, host might fall into some error
condition and ask from us the wrong Control phase.
On such situations, we should stall and restart.
Signed-off-by: Felipe Balbi <balbi@ti.com>

Whenever we issue a Set Stall command on EP0,
the state machine will be restarted and Stall
is cleared automatically, when core receives
the next SETUP packet.

There's no need to track that EP0_STALL state.
Signed-off-by: Felipe Balbi <balbi@ti.com>

when we're going to issue Set Stall command,
we should clear DWC3_EP_STALL flag, but also
we should clear BUSY, HALTED and all others.
Signed-off-by: Felipe Balbi <balbi@ti.com>

data was prepared on setup_buf but transfer
was started on ctrl_req, fix it.
Signed-off-by: Felipe Balbi <balbi@ti.com>

There are two spots where we wait until the HW finishes processing a
certain command. Initially we had a few problems and we used 500ms as a
limit to be on a the safe side. Paul Zimmerman mentioned this is little too
much. After a debugging session, we noticed that we hardly ever go over 20us
and didn't pass 30usec so far. Using mdelay() seems way overloaded.

Giving the current numbers 500usec as the upper limit is more than  enough.
Should it ever timeout then something is definitely wrong.

While here, also replace the type with u32 since long does not really
fit here.

Cc: Paul Zimmerman <paul.zimmerman@synopsys.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>

- since a while we are disabling an endpoint and purging every requests on
  RESET and DISCONNECT which leads to a warning since the endpoint was
  disabled twice (once by the UDC, and second time by the gadget). I
  think UDC should nuke all requests because all those requests
  become invalid. It's gadget driver's responsability, though, to disable
  its used endpoints. This is done by merging dwc3_stop_active_transfer()
  and dwc3_gadget_nuke_reqs() into dwc3_remove_requests().

- dwc3_stop_active_transfer() is now no longer called unconditionaly.
  This has the advantage that it is always called to disable an active
  transfer which means if res_trans_idx 0 than something went wrong and
  it is an error condition because we can't clean up the requests.

- Remove the DWC3_EP_WILL_SHUTDOWN which was introduced while
  introducing the command complete part for dequeue. All requests on
  req_queued list should be removed during the dwc3_cleanup_done_reqs()
  callback so there is no reason to go through the list again.
  We consider it an error condition if requests are still on this
  list since we never queue TRB without LST=1 (the last requests has
  always LST=1, there are no requests with LST=0 behind it).

[ balbi@ti.com : reworked commit log a bit, made patch apply ]
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>

We read the DWC3_GSNPSID register to make sure we got the correct
register offset passed. One of the recent commits moved the soft reset
before this so in case of the wrong offset we end up with "reset timed
out". This patch moves the "id" check before the reset again.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>

There are some issues around for enabling/disabling this mode and
handling it. It does not work perfectly (yet). However we have a few
gadgets tested successfuly so far. That means we are quite confident
that we won't need this in near future.
So I'm for removing it and bringing a working version back once there is
a need for it.

Thanks to Dan Carpenter who spotted the wrong memory handling here.

[ balbi@ti.com : made it actually apply ]

Cc: Dan Carpenter <error27@gmail.com>
Cc: wharms@bfs.de
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>

The DesignWare USB3 core tells us which phase
of a control transfer should be started, it
also tells us which physical endpoint needs
that transfer.

With these two informations, we have all we
need to simply EP0 handling quite a lot and
get rid rid of the SW state machine tracking
ep0 states.

For achieving this perfectly, we needed to
add support for situations where we get
XferNotReady while endpoint is still busy
and XferNotReady while gadget driver still
hasn't queued a request.
Signed-off-by: Felipe Balbi <balbi@ti.com>

Add a flag to keep track of ep0 direction.
This flag will be used on a following patch.
Signed-off-by: Felipe Balbi <balbi@ti.com>

In case we have transfers which aren't aligned
to wMaxPacketSize, we need to be careful with
how we start the transfer with the HW. OUT
transfers _must_ be aligned with wMaxPacketSize
and in order to guarantee that, we use a bounce
buffer.
Signed-off-by: Felipe Balbi <balbi@ti.com>

This core cannot handle OUT transfers which aren't
aligned to wMaxPacketSize, but that can happen at
least on control endpoint with the USB Audio Class.

This patch adds a bounce buffer to be used on the
case of a non-aligned ep0out request is queued.
Signed-off-by: Felipe Balbi <balbi@ti.com>

The status field of the Transfer Not Read event
is different on Control Endpoints. On this patch
we are just adding the defines to be used on a
later patch which will re-work the control endpoint
handling.
Signed-off-by: Felipe Balbi <balbi@ti.com>

the previous message had too little meaning. Make
it more human readable and use the macro we already
had for extracting the command completion status out
of DEPCMDn register.
Signed-off-by: Felipe Balbi <balbi@ti.com>

if we don't set DMA address to invalid when unmapping,
we might fall in a situation where request buffer
can't be mapped to DMA again.
Signed-off-by: Felipe Balbi <balbi@ti.com>

trivial patch. No functional changes.
Signed-off-by: Felipe Balbi <balbi@ti.com>

trivial patch, no functional changes
Signed-off-by: Felipe Balbi <balbi@ti.com>

We may as well fix this potential leak so we don't have to listen to
the static checkers complain.
Signed-off-by: Dan Carpenter <error27@gmail.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Without this patch we won't clear that bit and instead will
clear all other bits on our endpoint flag.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Type 6 should be used for the first transfer during an interval. This is
also what the reference driver is using. Type 7 seems to be for following
or additional transfers within the same interval.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>

If we collected two requests together (i.e. only the last of them has
LST=1) then we only have to stop transfer once: The clean-up code will
cleanup everything until first TRB with the LST bit set.
After XferComplete this index should be no longer valid since there is
no transfer pending.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>

A TRB which is dequeued seems to have its HWO bits set to 1. Therefore
we ignore it if we dequeue it after the command is completed.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Signed-off-by: Michal Sroczynski <msroczyn@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>