1. 21 Jun, 2015 1 commit
  2. 17 Jun, 2015 8 commits
  3. 11 Jun, 2015 1 commit
  4. 10 Jun, 2015 10 commits
    • Feng Kan's avatar
      i2c: busses: xgene-slimpro: fix incorrect __init declation for probe · d8453403
      Feng Kan authored
      Fix section mismatch error during kernel build for xgene_slimpro_i2c_probe
      function. It was incorrectly defined with __init declaration.
      Signed-off-by: default avatarFeng Kan <fkan@apm.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      d8453403
    • Alexander Sverdlin's avatar
      i2c: davinci: Avoid sending to own address · 41c8d452
      Alexander Sverdlin authored
      Sending a message to own address locks the controller up in very bizarre state,
      it behaves as slave even if MDR register clearly states master. The controller
      remains in this state until reset. To avoid unnecessary timeouts simply avoid
      sending to own address. The controller cannot do this any way. Also, do not
      enable AAS IRQ, as the slave mode is not supported by the driver and the only
      possibility to trigger this IRQ is to send to own address.
      Signed-off-by: default avatarAlexander Sverdlin <alexander.sverdlin@nokia.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      41c8d452
    • Alexander Sverdlin's avatar
      i2c: davinci: Refactor i2c_davinci_wait_bus_not_busy() · 72a956c5
      Alexander Sverdlin authored
      There are several problems in the function:
      - "to_cnt" variable does nothing
      - schedule_timeout() call without setting current state does nothing
      - "allow_sleep" parameter is not really used
      
      Refactor the function so that it really tries to wait. In case of timeout try
      to recover the bus.
      Signed-off-by: default avatarAlexander Sverdlin <alexander.sverdlin@nokia.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      72a956c5
    • Kamal Dasu's avatar
      i2c: brcmstb: Add Broadcom settop SoC i2c controller driver · dd1aa252
      Kamal Dasu authored
      Adding support for i2c controller driver for Broadcom settop
      SoCs.
      Signed-off-by: default avatarKamal Dasu <kdasu.kdev@gmail.com>
      [wsa: removed superfluous owner in platform_driver]
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      dd1aa252
    • Cyrille Pitchen's avatar
      i2c: at91: add support to FIFOs · 5e3cfc6c
      Cyrille Pitchen authored
      When FIFOs are available and enabled, the driver now configures the Atmel
      eXtended DMA Controller to perform word accesses instead of byte accesses
      when possible.
      The actual access width depends on the size of the buffer to transmit.
      
      To enable FIFO support the "atmel,fifo-size" property must be set properly
      in the I2C controller node of the device tree.
      Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
      Acked-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      5e3cfc6c
    • Cyrille Pitchen's avatar
      i2c: at91: print hardware version · 6ce461ea
      Cyrille Pitchen authored
      The probe() function now prints the hardware version of the I2C
      controller.
      Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
      [wsa: s/version/hw version/] for clarity]
      Acked-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      6ce461ea
    • Cyrille Pitchen's avatar
      i2c: at91: add support for new alternative command mode · 0ef6f321
      Cyrille Pitchen authored
      The alternative command mode was introduced to simplify the transmission
      of STOP conditions and to solve timing and latency issues around them.
      
      This mode relies on a new register, the Alternative Command Register,
      which must be set at the same time as the Master Mode Register. This new
      register was designed to allow simple setup of basic combined transactions
      built from up to two unitary transactions.
      
      Indeed, the ACR is split into two areas, which describe one unitary
      transaction each. Each area is filled with Data Length 8bit counter, a
      Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
      and is not supported by this driver yet. Also when using alternative
      command mode, the MREAD bit from the Master Mode Register is ignored.
      Instead the Direction bits from ACR are used to setup the direction, read
      or write, of each unitary transaction. Finally the 8bit counters must
      filled with the data length of their respective transaction. Then if only
      one transaction is to be used, the data length of the second one must be
      set to zero. At the moment, this driver uses only the first transaction.
      
      In addition to MMR and ACR, the Control Register also need to be written
      to enable the alternative command mode. That's the purpose of its ACMEN
      bit, which stands for Alternative Command Mode Enable.
      
      Note that the alternative command mode is compatible with the use of the
      Internal Address Register. So combined transactions for eeprom read are
      actually implemented with the Internal Address Register. This register is
      written with up to 3 bytes, which are the internal address sent to the
      slave through the first write transaction. Then the first area of the ACR
      describe the write transaction to follow, which carries the data to be
      read from the eeprom. The second area of the ACR is not used so its Data
      Length 8bit counter is cleared.
      
      For each byte sent or received by the device, the Data Length 8bit counter
      is decremented. When it reaches 0, a STOP condition is automatically sent.
      Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
      Acked-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      0ef6f321
    • Cyrille Pitchen's avatar
      i2c: at91: update documentation for DT bindings · 0ba82c95
      Cyrille Pitchen authored
      add a new value "atmel,sama5d2-i2c" for the "compatible" property.
      add a new optional property "atmel,fifo-size" to enable FIFO support when
      available.
      add missing optional properties "dmas" and "dma-names".
      Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
      Acked-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      0ba82c95
    • Cyrille Pitchen's avatar
      i2c: at91: use BIT() macro to define register bits · e84cf8f0
      Cyrille Pitchen authored
      This patch just fixes typo before applying later patches which will use
      register bits with index above 16.
      Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
      Acked-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      e84cf8f0
    • Cyrille Pitchen's avatar
      i2c: at91: fix a race condition when using the DMA controller · 93563a6a
      Cyrille Pitchen authored
      For TX transactions, the TXCOMP bit in the Status Register is cleared
      when the first data is written into the Transmit Holding Register.
      
      In the lines from at91_do_twi_transfer():
      at91_twi_write_data_dma(dev);
      at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
      
      the TXCOMP interrupt may be enabled before the DMA controller has
      actually started to write into the THR. In such a case, the TXCOMP bit
      is still set into the Status Register so the interrupt is triggered
      immediately. The driver understands that a transaction completion has
      occurred but this transaction hasn't started yet. Hence the TXCOMP
      interrupt is no longer enabled by at91_do_twi_transfer() but instead
      by at91_twi_write_data_dma_callback().
      
      Also, the TXCOMP bit in the Status Register in not a clear on read flag
      but a snapshot of the transmission state at the time the Status
      Register is read.
      When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
      and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
      interrupt is triggered at the same time. Also setting the TXRDY to 1
      triggers the DMA controller to write the next data into the THR. Such
      a write resets the TXCOMP bit to 0 in the SR. So depending on when the
      interrupt handler reads the SR, it may fail to detect the NACK error
      if it relies on the TXCOMP bit. The NACK bit and its interrupt should
      be used instead.
      
      For RX transactions, the TXCOMP bit in the Status Register is cleared
      when the START bit is set into the Control Register. However to unify
      the management of the TXCOMP bit when the DMA controller is used, the
      TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
      RX transfers.
      Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
      Cc: stable@vger.kernel.org #3.10 and later
      Acked-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      93563a6a
  5. 02 Jun, 2015 4 commits
  6. 31 May, 2015 10 commits
  7. 12 May, 2015 6 commits