- 30 Jan, 2008 40 commits
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Eric Dumazet authored
While examining vmlinux namelist on i386 (nm -v vmlinux) I noticed : c01021d0 t es7000_rename_gsi c010221a T es7000_start_cpu <Big Hole> c0103000 T thread_saved_pc and c0113218 T acpi_restore_state_mem c0113219 T acpi_save_state_mem <Big Hole> c0114000 t wakeup_code This is because arch/x86/kernel/acpi/wakeup_32.S forces a .text alignment of 4096 bytes. (I have no idea if it is really needed, since arch/x86/kernel/acpi/wakeup_64.S uses a 16 bytes alignment *only*) So arch/x86/kernel/built-in.o also has this alignment arch/x86/kernel/built-in.o: file format elf32-i386 Sections: Idx Name Size VMA LMA File off Algn 0 .text 00018c94 00000000 00000000 00001000 2**12 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE But as arch/x86/kernel/acpi/wakeup_32.o is not the first object linked into arch/x86/kernel/built-in.o, linker had to build several holes to meet alignement requirements, because of .o nestings in the kbuild process. This can be solved by using a special section, .text.page_aligned, so that no holes are needed. # size vmlinux.before vmlinux.after text data bss dec hex filename 4619942 422838 458752 5501532 53f25c vmlinux.before 4610534 422838 458752 5492124 53cd9c vmlinux.after This saves 9408 bytes Signed-off-by:Eric Dumazet <dada1@cosmosbay.com> Signed-off-by:
Ingo Molnar <mingo@elte.hu> Signed-off-by:
Thomas Gleixner <tglx@linutronix.de>
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Ingo Molnar authored
clean up include/asm-x86/calling.h. Signed-off-by:
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Andi Kleen authored
Otherwise WARNING: vmlinux.o(.text+0x64a9): Section mismatch: reference to .init.text:machine_specific_memory_setup (between 'memory_setup' and 'show_cpuinfo') Signed-off-by:
Andi Kleen <ak@suse.de> Signed-off-by:
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Andi Kleen authored
Someone complained that the 32-bit defconfig contains AS as default IO scheduler. Change that to CFQ. Signed-off-by:
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Andi Kleen authored
Previously the complete files were #ifdef'ed, but now handle that in the Makefile. May save a minor bit of compilation time. [ Stephen Rothwell <sfr@canb.auug.org.au>: build dependency fix ] Signed-off-by:
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Andi Kleen authored
Add missing targets and missing options in x86 make help [ mingo@elte.hu: more whitespace cleanups ] Signed-off-by:
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Andi Kleen authored
I don't know of any case where they have been useful and they look ugly. Signed-off-by:
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Andi Kleen authored
This is useful to debug problems with interrupt handlers that return sometimes IRQ_NONE. Signed-off-by:
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Andi Kleen authored
This allows to change them at runtime using sysfs. No need to reboot to set them. I only added aliases (kernel.noirqdebug etc.) so the old options still work. Signed-off-by:
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Jeremy Fitzhardinge authored
# HG changeset patch # User Jeremy Fitzhardinge <jeremy@xensource.com> # Date 1199391030 28800 # Node ID 5d35c92fdf0e2c52edbb6fc4ccd06c7f65f25009 # Parent 22f6a5902285b58bfc1fbbd9e183498c9017bd78 x86/efi: fix improper use of lvalue pgd_val is no longer valid as an lvalue, so don't try to assign to it. Signed-off-by:
Jeremy Fitzhardinge <jeremy@xensource.com> Signed-off-by:
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Jeremy Fitzhardinge authored
# HG changeset patch # User Jeremy Fitzhardinge <jeremy@xensource.com> # Date 1199321648 28800 # Node ID 22f6a5902285b58bfc1fbbd9e183498c9017bd78 # Parent bba9287641ff90e836d090d80b5c0a846aab7162 x86: page.h: move things back to their own files Oops, asm/page.h has turned into an #ifdef hellhole. Move 32/64-specific things back to their own headers to make it somewhat comprehensible... Signed-off-by:
Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by:
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Jeremy Fitzhardinge authored
# HG changeset patch # User Jeremy Fitzhardinge <jeremy@xensource.com> # Date 1199319657 28800 # Node ID bba9287641ff90e836d090d80b5c0a846aab7162 # Parent d617b72a0cc9d14bde2087d065c36d4ed3265761 x86: page.h: move remaining bits and pieces Move the remaining odds and ends into page.h. Signed-off-by:
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Jeremy Fitzhardinge authored
# HG changeset patch # User Jeremy Fitzhardinge <jeremy@xensource.com> # Date 1199319656 28800 # Node ID d617b72a0cc9d14bde2087d065c36d4ed3265761 # Parent 3bd7db6e85e66e7f3362874802df26a82fcb2d92 x86: page.h: move pa and va related things Move and unify the virtual<->physical address space conversion functions. Signed-off-by:
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Ingo Molnar authored
based on: Subject: x86: page.h: move and unify types for pagetable entry From: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by:
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Jeremy Fitzhardinge authored
# HG changeset patch # User Jeremy Fitzhardinge <jeremy@xensource.com> # Date 1199319654 28800 # Node ID 3bd7db6e85e66e7f3362874802df26a82fcb2d92 # Parent f7e7db3facd9406545103164f9be8f9ba1a2b549 x86: page.h: move and unify types for pagetable entry definitions This patch: 1. Defines arch-specific types for the contents of a pagetable entry. That is, 32-bit entries for 32-bit non-PAE, and 64-bit entries for 32-bit PAE and 64-bit. However, even though the latter two are the same size, they're defined with different types in order to retain compatibility with printk format strings, etc. 2. Defines arch-specific pte_t. This is different because 32-bit PAE defines it in two halves, whereas 32-bit PAE and 64-bit define it as a single entry. All the other pagetable levels can be defined in a common way. This also defines arch-specific pte_val/make_pte functions. 3. Define PAGETABLE_LEVELS for each architecture variation, for later use. 4. Define common pagetable entry accessors in a paravirt-compatible way. (64-bit does not yet use paravirt-ops in any way). 5. Convert a few instances of using a *_val() as an lvalue where it is no longer a macro. There are still places in the 64-bit code which use pte_val() as an lvalue. Signed-off-by:
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Ingo Molnar authored
based on: Subject: x86: page.h: move and unify types for pagetable entry From: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by:
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Ingo Molnar authored
Signed-off-by:
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Ingo Molnar authored
based on: Subject: x86: page.h: move and unify types for pagetable entry From: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by:
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Ingo Molnar authored
based on: Subject: x86: page.h: move and unify types for pagetable entry From: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by:
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Ingo Molnar authored
based on: Subject: x86: page.h: move and unify types for pagetable entry From: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by:
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Jeremy Fitzhardinge authored
# HG changeset patch # User Jeremy Fitzhardinge <jeremy@xensource.com> # Date 1199317452 28800 # Node ID f7e7db3facd9406545103164f9be8f9ba1a2b549 # Parent 4d9a413a0f4c1d98dbea704f0366457b5117045d x86: add _AT() macro to conditionally cast Define _AT(type, value) to conditionally cast a value when compiling C code, but not when used in assembler. Signed-off-by:
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Jeremy Fitzhardinge authored
# HG changeset patch # User Jeremy Fitzhardinge <jeremy@xensource.com> # Date 1199317362 28800 # Node ID 4d9a413a0f4c1d98dbea704f0366457b5117045d # Parent ba0ec40a50a7aef1a3153cea124c35e261f5a2df x86: page.h: unify page copying and clearing Move, and to some extent unify, the various page copying and clearing functions. The only unification here is that both architectures use the same function for copying/clearing user and kernel pages. Signed-off-by:
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Jeremy Fitzhardinge authored
# HG changeset patch # User Jeremy Fitzhardinge <jeremy@xensource.com> # Date 1199317360 28800 # Node ID ba0ec40a50a7aef1a3153cea124c35e261f5a2df # Parent c45c263179cb78284b6b869c574457df088027d1 x86: page.h: unify constants There are many constants which are shared by 32 and 64-bit. Signed-off-by:
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Andreas Herrmann authored
Commits - c52f61fcbdb2aa84f0e4d831ef07f375e6b99b2c (x86: allow TSC clock source on AMD Fam10h and some cleanup) - e30436f05d456efaff77611e4494f607b14c2782 (x86: move X86_FEATURE_CONSTANT_TSC into early cpu feature detection) are supposed to fix the detection of contant TSC for AMD CPUs. Unfortunately on x86_64 it does still not work with current x86/mm. For a Phenom I still get: ... TSC calibrated against PM_TIMER Marking TSC unstable due to TSCs unsynchronized time.c: Detected 2288.366 MHz processor. ... We have to set c->x86_power in early_identify_cpu to properly detect the CONSTANT_TSC bit in early_init_amd. Attached patch fixes this issue. Following the relevant boot messages when the fix is used: ... TSC calibrated against PM_TIMER time.c: Detected 2288.279 MHz processor. ... Initializing CPU#1 ... checking TSC synchronization [CPU#0 -> CPU#1]: passed. ... Initializing CPU#2 ... checking TSC synchronization [CPU#0 -> CPU#2]: passed. ... Booting processor 3/4 APIC 0x3 ... checking TSC synchronization [CPU#0 -> CPU#3]: passed. Brought up 4 CPUs ... Patch is against x86/mm (v2.6.24-rc8-672-ga9f7faa). Please apply. Set c->x86_power in early_identify_cpu. This ensures that X86_FEATURE_CONSTANT_TSC can properly be set in early_init_amd. Signed-off-by:
Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by:
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Andi Kleen authored
The ACPI code currently disables TSC use in any C2 and C3 states. But the AMD Fam10h BKDG documents that the TSC will never stop in any C states when the CONSTANT_TSC bit is set. Make this disabling conditional on CONSTANT_TSC not set on AMD. I actually think this is true on Intel too for C2 states on CPUs with p-state invariant TSC, but this needs further discussions with Len to really confirm :-) So far it is only enabled on AMD. Cc: lenb@kernel.org Signed-off-by:
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Andi Kleen authored
Trust the ACPI code to disable TSC instead when C3 is used. AMD Fam10h does not disable TSC in any C states so the check was incorrect there anyways after the change to handle this like Intel on AMD too. This allows to use the TSC when C3 is disabled in software (acpi.max_c_state=2), but the BIOS supports it anyways. Match i386 behaviour. Cc: lenb@kernel.org Signed-off-by:
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Andi Kleen authored
After a lot of discussions with AMD it turns out that TSC on Fam10h CPUs is synchronized when the CONSTANT_TSC cpuid bit is set. Or rather that if there are ever systems where that is not true it would be their BIOS' task to disable the bit. So finally use TSC gettimeofday on Fam10h by default. Or rather it is always used now on CPUs where the AMD specific CONSTANT_TSC bit is set. This gives a nice speed bost for gettimeofday() on these systems which tends to be by far the most common v/syscall. On a Fam10h system here TSC gtod uses about 20% of the CPU time of acpi_pm based gtod(). This was measured on 32bit, on 64bit it is even better because TSC gtod() can use a vsyscall and stay in ring 3, which acpi_pm doesn't. The Intel check simply checks for CONSTANT_TSC too without hardcoding Intel vendor. This is equivalent on 64bit because all 64bit capable Intel CPUs will have CONSTANT_TSC set. On Intel there is no CPU supplied CONSTANT_TSC bit currently, but we synthesize one based on hardcoded knowledge which steppings have p-state invariant TSC. So the new logic is now: On CPUs which have the AMD specific CONSTANT_TSC bit set or on Intel CPUs which are new enough to be known to have p-state invariant TSC always use TSC based gettimeofday() Cc: lenb@kernel.org Signed-off-by:
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Andi Kleen authored
Need this in the next patch in time_init and that happens early. This includes a minor fix on i386 where early_intel_workarounds() [which is now called early_init_intel] really executes early as the comments say. Signed-off-by:
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Andi Kleen authored
we need to know whether RDTSC is synchronous or not. Signed-off-by:
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Ingo Molnar authored
[ andi@firstfloor.org: build fix ] Signed-off-by:
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Andi Kleen authored
rdtsc is now speculation-safe, so no need for the sync variants of the APIs. [ mingo@elte.hu: removed the nsec_barrier() complication. ] Signed-off-by:
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Ingo Molnar authored
make native_read_tsc() always non-speculative. Signed-off-by:
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Ingo Molnar authored
map vsyscalls early enough. This is important if a __vsyscall_fn function is used by other kernel code too. Signed-off-by:
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Ingo Molnar authored
move native_read_tsc() offline. Signed-off-by:
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Andi Kleen authored
rdtsc_barrier() is a new barrier primitive that stops RDTSC speculation to avoid races with timer interrupts on other CPUs. It expands either to LFENCE (for Intel CPUs) or MFENCE (for AMD CPUs) which stops RDTSC on all currently known microarchitectures that implement SSE. On CPUs without SSE there is generally no RDTSC speculation. [ mingo@elte.hu: renamed it to rdtsc_barrier() and made it x86-only ] Signed-off-by:
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WANG Cong authored
Acked-by:
Jeff Dike <jdike@addtoit.com> Signed-off-by:
WANG Cong <xiyou.wangcong@gmail.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Andi Kleen authored
Moving things out of processor.h is always a good thing. Also needed to avoid include loop in later patch. Signed-off-by:
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Ingo Molnar authored
LFENCE is available on XMM2 or higher Intel CPUs - not XMM or higher... this caused boot failures on XMM1 & !XMM1 capable CPUs. Signed-off-by:
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Andi Kleen authored
According to Intel RDTSC can be always synchronized with LFENCE on all current CPUs. Implement the necessary CPUID bit for that. It is unclear yet if that is true for all future CPUs too, but if there's another way the kernel can be always updated. Cc: asit.k.mallick@intel.com Signed-off-by:
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Andi Kleen authored
According to AMD RDTSC can be synchronized through MFENCE. Implement the necessary CPUID bit for that. Cc: andreas.herrmann3@amd.com Signed-off-by:
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