- 10 Jun, 2009 40 commits
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Jes Sorensen authored
Preserve interrupt status around call to kvm_insert_vmm_mappin() in kvm_vcpu_pre_transition(). Signed-off-by:
Jes Sorensen <jes@sgi.com> Acked-by:
Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by:
Avi Kivity <avi@redhat.com>
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Jes Sorensen authored
Make sure to restore the psr after calling kvm_insert_vmm_mapping() which calls ia64_itr_entry() as it disables local interrupts and kvm_vcpu_init() may sleep. Avoids a warning from the lock debugging code. Signed-off-by:
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Jes Sorensen authored
vti_vcpu_load() doesn't do anything, so lets get rid of it. Signed-off-by:
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Xiantao Zhang authored
Flush all vcpu's TLB entries once changes guest's memory mapping. Signed-off-by:
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Marcelo Tosatti authored
Matt T. Yourst notes that kvm_arch_vcpu_ioctl_set_sregs lacks validity checking for the new cr3 value: "Userspace callers of KVM_SET_SREGS can pass a bogus value of cr3 to the kernel. This will trigger a NULL pointer access in gfn_to_rmap() when userspace next tries to call KVM_RUN on the affected VCPU and kvm attempts to activate the new non-existent page table root. This happens since kvm only validates that cr3 points to a valid guest physical memory page when code *inside* the guest sets cr3. However, kvm currently trusts the userspace caller (e.g. QEMU) on the host machine to always supply a valid page table root, rather than properly validating it along with the rest of the reloaded guest state." http://sourceforge.net/tracker/?func=detail&atid=893831&aid=2687641&group_id=180599 Check for a valid cr3 address in kvm_arch_vcpu_ioctl_set_sregs, triple fault in case of failure. Cc: stable@kernel.org Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by:
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Jes Sorensen authored
Reorder locking to avoid holding the slots_lock when entering the guest. Signed-off-by:
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Avi Kivity authored
Suggested by Ingo Molnar. Signed-off-by: -
Gleb Natapov authored
If a task switch was initiated because off a task gate in IDT and IDT was accessed because of an external even the instruction should not be skipped. Signed-off-by:
Gleb Natapov <gleb@redhat.com> Signed-off-by:
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Gleb Natapov authored
In the new mode instruction is decoded, but not executed. The EIP is moved to point after the instruction. Signed-off-by:
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Gleb Natapov authored
Do not emulate them yet. Signed-off-by:
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Gleb Natapov authored
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Gleb Natapov authored
Extend "Source operand type" opcode description field to 4 bites to accommodate new option. Signed-off-by:
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Gleb Natapov authored
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Gleb Natapov authored
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Gleb Natapov authored
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Gleb Natapov authored
No emulation yet. Signed-off-by:
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Gleb Natapov authored
Such as segment number in lcall/ljmp Signed-off-by:
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Marcelo Tosatti authored
Complexity to fix it not worthwhile the gains, as discussed in http://article.gmane.org/gmane.comp.emulators.kvm.devel/28649. Signed-off-by:
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nathan binkert authored
Two things needed fixing: 1) g++ does not allow a named structure type within an anonymous union and 2) Avoid name clash between two padding fields within the same struct by giving them different names as is done elsewhere in the header. Signed-off-by:
Nathan Binkert <nate@binkert.org> Signed-off-by:
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Marcelo Tosatti authored
Commit 46ee278652f4cbd51013471b64c7897ba9bcd1b1 causes Solaris 10 to hang on boot. Assuming that PIT counter reads should return 0 for an expired timer is wrong: when it is active, the counter never stops (see comment on __kpit_elapsed). Also arm a one shot timer for mode 0. Signed-off-by:
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Zhang, Xiantao authored
Since kvm-intel modue can't be built-in, make kvm depend on CONFIG_MODULES. Signed-off-by:
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Gleb Natapov authored
The length of pushed on to the stack return address depends on operand size not address size. Signed-off-by:
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Sheng Yang authored
1. It's related to a Linux kernel bug which fixed by Ingo on 07a66d7c. The original code exists for quite a long time, and it would convert a PDE for large page into a normal PDE. But it fail to fit normal PDE well. With the code before Ingo's fix, the kernel would fall reserved bit checking with bit 8 - the remaining global bit of PTE. So the kernel would receive a double-fault. 2. After discussion, we decide to discard PDE bit 7-8 reserved checking for now. For this marked as reserved in SDM, but didn't checked by the processor in fact... Signed-off-by:
Sheng Yang <sheng@linux.intel.com> Signed-off-by:
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Gleb Natapov authored
There is no need to skip instruction if the reason for a task switch is a task gate in IDT and access to it is caused by an external even. The problem is currently solved only for VMX since there is no reliable way to skip an instruction in SVM. We should emulate it instead. Signed-off-by:
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Gleb Natapov authored
Back link is written to a wrong TSS now. Signed-off-by:
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Gleb Natapov authored
We will need it later in task_switch(). Code in handle_exception() is dead. is_external_interrupt(vect_info) will always be false since idt_vectoring_info is zeroed in vmx_complete_interrupts(). Signed-off-by:
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Gleb Natapov authored
...with a more straightforward switch(). Also fix a bug when NMI could be dropped on exit. Although this should never happen in practice, since NMIs can only be injected, never triggered internally by the guest like exceptions. Signed-off-by:
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Gleb Natapov authored
Bit 12 is undefined in any of the following cases: If the VM exit sets the valid bit in the IDT-vectoring information field. If the VM exit is due to a double fault. Signed-off-by:
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Dong, Eddie authored
Also remove bit 5-6 from rsvd_bits_mask per latest SDM. Signed-off-by:
Eddie Dong <Eddie.Dong@intel.com> Signed-off-by:
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Sheng Yang authored
The testing of feature is too early now, before vmcs_config complete initialization. Signed-off-by:
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Sheng Yang authored
And clean paranthes on returns. Signed-off-by:
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Wei Yongjun authored
Remove pointless conditional before kfree(). Signed-off-by:
Wei Yongjun <yjwei@cn.fujitsu.com> Signed-off-by:
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Avi Kivity authored
A pte that is shadowed when the guest EFER.NXE=1 is not valid when EFER.NXE=0; if bit 63 is set, the pte should cause a fault, and since the shadow EFER always has NX enabled, this won't happen. Fix by using a different shadow page table for different EFER.NXE bits. This allows vcpus to run correctly with different values of EFER.NXE, and for transitions on this bit to be handled correctly without requiring a full flush. Signed-off-by: -
Dong, Eddie authored
Detect, indicate, and propagate page faults where reserved bits are set. Take care to handle the different paging modes, each of which has different sets of reserved bits. [avi: fix pte reserved bits for efer.nxe=0] Signed-off-by:
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Yang Zhang authored
Currently, the interrupt enable bit is cleared when in the vmm. This patch sets the bit and the external interrupts can be dealt with when in the vmm. This improves the I/O performance. Signed-off-by:
Yang Zhang <yang.zhang@intel.com> Signed-off-by:
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Eddie Dong authored
The original one is for the code before refactoring. Signed-off-by:
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Sheng Yang authored
EXIT_QUALIFICATION and GUEST_LINEAR_ADDRESS are natural width, not 64-bit. Signed-off-by:
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Avi Kivity authored
If the hardware does not support flexpriority, zero the module parameter. Signed-off-by: -
Gleb Natapov authored
kvm_vcpu_block() unhalts vpu on an interrupt/timer without checking if interrupt window is actually opened. Signed-off-by:
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Gleb Natapov authored
Currently timer events are processed before entering guest mode. Move it to main vcpu event loop since timer events should be processed even while vcpu is halted. Timer may cause interrupt/nmi to be injected and only then vcpu will be unhalted. Signed-off-by:
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