1. 14 Oct, 2016 8 commits
    • Zhi Wang's avatar
      drm/i915/gvt: vGPU PCI configuration space virtualization · 4d60c5fd
      Zhi Wang authored
      This patch introduces vGPU PCI configuration space virtualization.
      
      - Adjust the trapped GPFN(Guest Page Frame Number) window of virtual GEN
      PCI BAR 0 when guest initializes PCI BAR 0 address.
      
      - Emulate OpRegion when guest touches OpRegion.
      
      - Pass-through a part of aperture to guest when guest initializes
      aperture BAR.
      Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      4d60c5fd
    • Zhi Wang's avatar
      drm/i915/gvt: vGPU graphics memory virtualization · 2707e444
      Zhi Wang authored
      The vGPU graphics memory emulation framework is responsible for graphics
      memory table virtualization. Under virtualization environment, a VM will
      populate the page table entry with guest page frame number(GPFN/GFN), while
      HW needs a page table filled with MFN(Machine frame number). The
      relationship between GFN and MFN(Machine frame number) is managed by
      hypervisor, while GEN HW doesn't have such knowledge to translate a GFN.
      
      To solve this gap, shadow GGTT/PPGTT page table is introdcued.
      
      For GGTT, the GFN inside the guest GGTT page table entry will be translated
      into MFN and written into physical GTT MMIO registers when guest write
      virtual GTT MMIO registers.
      
      For PPGTT, a shadow PPGTT page table will be created and write-protected
      translated from guest PPGTT page table.  And the shadow page table root
      pointers will be written into the shadow context after a guest workload
      is shadowed.
      
      vGPU graphics memory emulation framework consists:
      
      - Per-GEN HW platform page table entry bits extract/de-extract routines.
      - GTT MMIO register emulation handlers, which will call hypercall to do
      GFN->MFN translation when guest write GTT MMIO register
      - PPGTT shadow page table routines, e.g. shadow create/destroy/out-of-sync
      Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      2707e444
    • Zhi Wang's avatar
      drm/i915/gvt: vGPU interrupt virtualization. · c8fe6a68
      Zhi Wang authored
      This patch introduces vGPU interrupt emulation framework.
      
      The vGPU intrerrupt emulation framework is an event-based interrupt
      emulation framework. It's responsible for emulating GEN hardware interrupts
      during emulating other HW behaviour.
      
      It consists several components:
      
      - Descriptions of interrupt register bit
      - Upper level <-> lower level interrupt mapping
      - GEN HW IER/IMR/IIR register emulation routines
      - Event-based interrupt propagation interface
      
      When a GVT-g component wants to inject an interrupt to a VM during a
      emulation, first it should specify the event needs to be emulated and the
      framework will deal with the rest of emulation:
      
      - Generating related virtual IIR bit according to virtual IER and IMRs,
      - Generate related virtual upper level virtual IIR bit accodring to the
      per-platform interrupt mapping
      - Injecting a MSI to VM
      Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      c8fe6a68
    • Zhi Wang's avatar
      drm/i915/gvt: trace stub · 3f728236
      Zhi Wang authored
      v2:
      - Make checkpatch.pl happy(Joonas)
      Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      3f728236
    • Zhi Wang's avatar
      drm/i915/gvt: Introduce basic vGPU life cycle management · 82d375d1
      Zhi Wang authored
      A vGPU represents a virtual Intel GEN hardware, which consists following
      virtual resources:
      
      - Configuration space (virtualized)
      - HW registers (virtualized)
      - GGTT memory space (partitioned)
      - GPU page table (shadowed)
      - Fence registers (partitioned)
      
      * virtualized: fully emulated by GVT-g.
      * partitioned: Only a part of the HW resource is allowed to be accessed
      by VM.
      * shadowed: Resource needs to be translated and shadowed before getting
      applied into HW.
      
      This patch introduces vGPU life cycle management framework, which is
      responsible for creating/destroying a vGPU and preparing/free resources
      related to a vGPU.
      Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      82d375d1
    • Zhi Wang's avatar
      drm/i915/gvt: golden virtual HW state management · 579cea5f
      Zhi Wang authored
      Each vGPU expects a golden virtual HW state, which is just the state after
      system is freshly powered on. GVT-g will try to load the golden virtual HW
      state via kernel firmware interface.
      Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      579cea5f
    • Zhi Wang's avatar
      drm/i915/gvt: Introduce a framework for tracking HW registers. · 12d14cc4
      Zhi Wang authored
      This patch introduces a framework for tracking HW registers on different
      GEN platforms.
      
      Accesses to GEN HW registers from VMs will be trapped by hypervisor. It
      will forward these emulation requests to GVT-g device model, which
      requires this framework to search for related register descriptions.
      
      Each MMIO entry in this framework describes a GEN HW registers, e.g.
      offset, length, whether it contains RO bits, whether it can be accessed by
      LRIs...and also emulation handlers for emulating register reading and
      writing.
      
      - Use i915 MMIO register definition & statement.(Joonas)
      Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      12d14cc4
    • Zhi Wang's avatar
      drm/i915/gvt: vGPU HW resource management · 28a60dee
      Zhi Wang authored
      This patch introduces the GVT-g vGPU HW resource management. Under
      GVT-g virtualizaion environment, each vGPU requires portions HW
      resources, including aperture, hidden GM space, and fence registers.
      
      When creating a vGPU, GVT-g will request these HW resources from host,
      and return them to host after a vGPU is destroyed.
      Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
      28a60dee
  2. 13 Oct, 2016 10 commits
  3. 12 Oct, 2016 11 commits
  4. 11 Oct, 2016 11 commits