- 06 Jan, 2007 40 commits
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Avi Kivity authored
It overwrites the right cr3 set from mmu setup. Happens only with the test harness. Signed-off-by:
Avi Kivity <avi@qumranet.com> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Avi Kivity authored
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Ingo Molnar authored
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Ingo Molnar <mingo@elte.hu> Signed-off-by:
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Avi Kivity authored
Fixes oops on early close of /dev/kvm. Signed-off-by:
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Avi Kivity authored
This will allow us to see the root cause when a vmwrite error happens. Signed-off-by:
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Avi Kivity authored
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Avi Kivity authored
mmu_destroy flushes the guest tlb (indirectly), which needs a valid vcpu. Signed-off-by:
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Avi Kivity authored
If we reduce permissions on a pte, we must flush the cached copy of the pte from the guest's tlb. This is implemented at the moment by flushing the entire guest tlb, and can be improved by flushing just the relevant virtual address, if it is known. Signed-off-by:
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Avi Kivity authored
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Avi Kivity authored
The mmu sometimes needs memory for reverse mapping and parent pte chains. however, we can't allocate from within the mmu because of the atomic context. So, move the allocations to a central place that can be executed before the main mmu machinery, where we can bail out on failure before any damage is done. (error handling is deffered for now, but the basic structure is there) Signed-off-by:
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Avi Kivity authored
Because mmu pages have attached rmap and parent pte chain structures, we need to zap them before freeing so the attached structures are freed. Signed-off-by:
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Avi Kivity authored
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Avi Kivity authored
cmpxchg8b uses edx:eax as the compare operand, not edi:eax. cmpxchg8b is used by 32-bit pae guests to set page table entries atomically, and this is emulated touching shadowed guest page tables. Also, implement it for 32-bit hosts. Signed-off-by:
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Avi Kivity authored
We always need cr3 to point to something valid, so if we detect that we're freeing a root page, simply push it back to the top of the active list. Signed-off-by:
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Avi Kivity authored
In fork() (or when we protect a page that is no longer a page table), we can experience floods of writes to a page, which have to be emulated. This is expensive. So, if we detect such a flood, zap the page so subsequent writes can proceed natively. Signed-off-by:
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Avi Kivity authored
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Avi Kivity authored
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Avi Kivity authored
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Avi Kivity authored
A misaligned access affects two shadow ptes instead of just one. Since a misaligned access is unlikely to occur on a real page table, just zap the page out of existence, avoiding further trouble. Signed-off-by:
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Avi Kivity authored
Unused. Signed-off-by:
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Avi Kivity authored
Since we write protect shadowed guest page tables, there is no need to trap page invalidations (the guest will always change the mapping before issuing the invlpg instruction). Signed-off-by:
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Avi Kivity authored
When beginning to process a page fault, make sure we have enough shadow pages available to service the fault. If not, free some pages. Signed-off-by:
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Avi Kivity authored
... and so must not free it unconditionally. Move the freeing to kvm_mmu_zap_page(). Signed-off-by:
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Avi Kivity authored
When removing a page table, we must maintain the parent_pte field all child shadow page tables. Signed-off-by:
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Avi Kivity authored
A page table may have been recycled into a regular page, and so any instruction can be executed on it. Unprotect the page and let the cpu do its thing. Signed-off-by:
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Avi Kivity authored
Iterate over all shadow pages which correspond to a the given guest page table and remove the mappings. A subsequent page fault will reestablish the new mapping. Signed-off-by:
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Avi Kivity authored
As the mmu write protects guest page table, we emulate those writes. Since they are not mmio, there is no need to go to userspace to perform them. So, perform the writes in the kernel if possible, and notify the mmu about them so it can take the approriate action. Signed-off-by:
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Avi Kivity authored
This fixes a problem where set_pte_common() looked for shadowed pages based on the page directory gfn (a huge page) instead of the actual gfn being mapped. Signed-off-by:
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Avi Kivity authored
When we cache a guest page table into a shadow page table, we need to prevent further access to that page by the guest, as that would render the cache incoherent. Signed-off-by:
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Avi Kivity authored
Define a hashtable for caching shadow page tables. Look up the cache on context switch (cr3 change) or during page faults. The key to the cache is a combination of - the guest page table frame number - the number of paging levels in the guest * we can cache real mode, 32-bit mode, pae, and long mode page tables simultaneously. this is useful for smp bootup. - the guest page table table * some kernels use a page as both a page table and a page directory. this allows multiple shadow pages to exist for that page, one per level - the "quadrant" * 32-bit mode page tables span 4MB, whereas a shadow page table spans 2MB. similarly, a 32-bit page directory spans 4GB, while a shadow page directory spans 1GB. the quadrant allows caching up to 4 shadow page tables for one guest page in one level. - a "metaphysical" bit * for real mode, and for pse pages, there is no guest page table, so set the bit to avoid write protecting the page. Signed-off-by: -
Avi Kivity authored
This allows further manipulation on the shadow page table. Signed-off-by:
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Avi Kivity authored
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Avi Kivity authored
This lets us not write protect a partial page, and is anyway what a real processor does. Signed-off-by:
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Avi Kivity authored
Since we're not going to cache the pae-mode shadow root pages, allocate a single pae shadow that will hold the four lower-level pages, which will act as roots. Signed-off-by:
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Avi Kivity authored
It is never necessary to fetch a guest entry from an intermediate page table level (except for large pages), so avoid some confusion by always descending into the lowest possible level. Rename init_walker() to walk_addr() as it is no longer restricted to initialization. Signed-off-by:
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Avi Kivity authored
In pae mode, a load of cr3 loads the four third-level page table entries in addition to cr3 itself. Signed-off-by:
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Avi Kivity authored
Saving the table gfns removes the need to walk the guest and host page tables in lockstep. Signed-off-by:
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Avi Kivity authored
Keep in each host page frame's page->private a pointer to the shadow pte which maps it. If there are multiple shadow ptes mapping the page, set bit 0 of page->private, and use the rest as a pointer to a linked list of all such mappings. Reverse mappings are needed because we when we cache shadow page tables, we must protect the guest page tables from being modified by the guest, as that would invalidate the cached ptes. Signed-off-by:
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Avi Kivity authored
Hardware virtualization implementations allow the guests to freely change some of the bits in cr0 and cr4, but trap when changing the other bits. This is useful to avoid excessive exits due to changing, for example, the ts flag. It also means the kvm's copy of cr0 and cr4 may be stale with respect to these bits. most of the time this doesn't matter as these bits are not very interesting. Other times, however (for example when returning cr0 to userspace), they are, so get the fresh contents of these bits from the guest by means of a new arch operation. Signed-off-by:
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David Brownell authored
Bugfixes: - Handle RTCs which are configured to use 12-hour mode. - Never report bogus/un-initialized times. - Displaying "raw trim" requires not masking it first! - Fix the sysfs and procfs display of crystal and trim data. Features: - Handle other RTCs in this family, notably rv5c386/rv5c387. - Declare the other registers. - Provide alarm get/set functionality. - Handle AIE and UIE; but no IRQ handling yet. Cleanup: - Shrink object by not including needless sysfs or procfs support - We don't need no steenkin' forward declarations. (Except one.) Until the I2C framework merges "new style" driver support, matching the driver model better, using rv5c chips or alarm IRQs requires a separate board-specific patch. (And an IRQ handler, handing off labor through a work_struct...) This uses the "method 3" register reads, but notes that it's done to work around an evident i2c adapter driver bug. Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net> Acked-by:
Alessandro Zummo <a.zummo@towertech.it> Signed-off-by:
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