- 21 Jun, 2022 1 commit
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Ruijing Dong authored
- add unified queue headers - add unified queue ib tests Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
Ruijing Dong <ruijing.dong@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 15 Jun, 2022 36 commits
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Rodrigo Siqueira authored
Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Alex Deucher authored
Use the same pattern as the DML Makefile and while we are here add a missing x86 guard around the msse flags for DCN3.2.x. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
This reverts commit d8e4fb91. This is no longer necessary as newer patches require these functions without CONFIG_DRM_AMD_DC_DCN. Reviewed-by:
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Alex Deucher authored
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1542:11: warning: variable 'i' set but not used [-Wunused-but-set-variable] Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Yifan Zhang authored
enable_mes and enable_mes_kiq are set in both device init and MES IP init. Leave the ones in MES IP init, since it is a more accurate way to judge from GC IP version. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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Joshua Aberback authored
[Why] All displays need to be blanked during the uclk OC interface so that we can guarantee pstate switching support. If the display config doesn't support pstate switching, only using core_link_disable_stream will not enable it as the front-end is untouched. We need to go through the full plane removal sequence to properly program the pipe to allow pstate switching. [How] - guard clk_mgr functions with non-NULL checks Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Martin Leung authored
[why] dc_submit_i2c_oem could be called with ddc null [how] add null check and fail the call instead Acked-by:
Martin Leung <martin.leung@amd.com> Tested-by:
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Charlene Liu authored
[why] need to add timing adjustment for fva. [how] add hook to optc and hwseq. Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Harry VanZyllDeJong authored
[WHY] The display driver on some OSes need to track it in order to perform memory clock switching decisions. [HOW] Propagate the vrr active state to dirty bit so that on mode set it disables dynamic memory clock switching. Acked-by:
Harry VanZyllDeJong <harry.vanzylldejong@amd.com> Tested-by:
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Felipe Clark authored
[WHY] New features will require knowing the vrr mode for their enablement. [HOW] Pass the state via a member of dc_stream. Acked-by:
Felipe Clark <Felipe.Clark@amd.com> Tested-by:
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Ahmad Othman authored
[Why] Video Timing Extended Metadata packet (VTEM) is required for features like VRR and FVA [How] Adding support for VTEM transmission to stream encoders in DCN20 and DCN30 as part of FVA support Acked-by:
Ahmad Othman <ahmad.othman@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why & How] Miss to copy hfvsif_infopacket when copying stream updates. Check and copy it. Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Ahmad Othman authored
[Why] - Currently there is no support for HF-VSIF - The current support of VSIF is limited to H14b infoframe [How] - refactor VSIF - Added new builder for HF-VSIF - Added the HF-VSIF packet to DisplayTarget - Updates DC to apply HF-VSIF updates when updating streams Acked-by:
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Felipe Clark authored
[WHY] Memory clock switching has great potential for power savings. [HOW] The driver code was modified to notify the DMCUB firmware that it should stretch the vertical blank of frames when a memory clock switch is about to start so that no blackouts happen on the screen due to unavailability of the frame buffer. The driver logic to determine when such firmware assisted strategy can be initiated is also implemented and consists on checking prerequisites of the feature. Acked-by:
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Ian Chen authored
[Why] - missing in dcn30 function - Fix a divide by 0 when ACR trigger [How] - Add IS_SMU_TIMEOUT() to dcn30_smu_send_msg_with_param - Add zero check in dcn20_update_clocks_update_dentist Acked-by:
Ian Chen <ian.chen@amd.com> Tested-by:
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Samson Tam authored
[Why & how] Fix format and typo of comments. Acked-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Oliver Logush authored
[Why and How] dwbc_funcs.set/get_privacy_mask isn't being used anymore, drop it Reviewed-by:
Oliver Logush <oliver.logush@amd.com> Tested-by:
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Aric Cyr authored
This version brings along the following: - DP fixes - Exiting idle optimizations on mouse updates Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Qingqing Zhuo authored
[Why] DIO parameters were missing in topology_update_intput_v3 struct. [How] Add DIO parameters in v3 struct and update in functions perspectively. Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Have option to exit idle opt on cursor updates for debug and optimizations purposes Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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hersen wu authored
[Why] when 4k@144hz dp connect to dp1.4 dsc mst hub, requested bandwidth exceeds caps of dsc hub. but dsc bw valid functions, increase_dsc_bpp, try_disable_dsc, pre_validate_dsc, compute_mst_dsc_configs_for_state, do not return false to atomic check. this cause user mode initiate mode set to kernel, then cause kernel assert, system hang. [How] dsc bandwidth valid functions return pass or fail to atomic check. Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
hersen wu <hersenxs.wu@amd.com> Tested-by:
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Shah Dharati authored
[Why & How] For a some specific monitors, when connected on boot or hot plug, monitor flash for 1/2 seconds can happen during first HDCP query operation. Ading some delay in the init sequence for these monitors fixes the issue, so it is implemented as monitor specific patch. Co-authored-by:
Shah Dharati <dharshah@amd.com> Reviewed-by:
Hansen Dsouza <Hansen.Dsouza@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] According to DP specs, in EQ DONE phase of link training, we should lower lane count when at least one CR DONE bit is set to 1, while lower link rate when all CR DONE bits are 0s. However in our code, we will treat both cases as latter. This is not exactly correct based on the specs expectation. [how] Check lane0 CR DONE bit when it is still set but CR DONE fails, we treat it as a partial CR DONE failure in EQ DONE phase, we will follow the same fallback flow as when ED DONE fails in EQ DONE phase. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Daniel Phillips authored
Add a new KFD ioctl to return the largest possible memory size that can be allocated as a buffer object using kfd_ioctl_alloc_memory_of_gpu. It attempts to use exactly the same accept/reject criteria as that function so that allocating a new buffer object of the size returned by this new ioctl is guaranteed to succeed, barring races with other allocating tasks. This IOCTL will be used by libhsakmt: https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg75743.htmlSigned-off-by:
Daniel Phillips <Daniel.Phillips@amd.com> Signed-off-by:
David Yat Sin <David.YatSin@amd.com> Reviewed-by:
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Chengming Gui authored
This reverts commit 2cfe34e1. Enable AGP aperture cause SDMA page fault for gfx11.0.2, so temp disable AGP aperture until SDMA FW resolved this. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
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Evan Quan authored
Enable BAMACO reset support for SMU 13.0.0. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
The feature is ready with latest PMFW and IFWI. Signed-off-by:
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Aurabindo Pillai authored
[Why&How] To reduce stack usage, move some variables into heap in the DML function dml32_ModeSupportAndSystemConfigurationFull() Fixes: dda4fb85 ("drm/amd/display: DML changes for DCN32/321") Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
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Leo Li authored
[Why] There is a theoretical problem in prior patches for reducing the stack size of *update_bw_bounding_box() functions. By modifying the soc.clock_limits[n] struct directly, this can cause unintended behavior as the for loop attempts to swap rows in clock_limits[n]. A temporary struct is still required to make sure we stay functinoally equivalent. [How] Add a temporary clock_limits table to the SOC struct, and use it when swapping rows. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
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Michel Dänzer authored
The commit below changed the TTM manager size unit from pages to bytes, but failed to adjust the corresponding calculations in amdgpu_ioctl. Fixes: dfa714b8 ("drm/amdgpu: remove GTT accounting v2") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1930 Bug: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6642Tested-by:
Martin Roukala <martin.roukala@mupuf.org> Tested-by:
Mike Lothian <mike@fireburn.co.uk> Reviewed-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Tim Huang authored
The EnableGfxImu message will be issued in the set_gfx_power_up_by_imu. Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
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Tim Huang authored
For SMU IP v13.0.4, the smnMP1_FIRMWARE_FLAGS address is different, we need this to correct the reading address. Signed-off-by:
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Aurabindo Pillai authored
[Why&How] There are cases where swizzle modes are set but modifiers arent. For such a userspace, we need not check modifiers while checking compatibilty in the drm hook for checking plane format. Ignore checking modifiers but check the DCN generation for the supported swizzle mode. v2: squash in unused variable removal (Alex) Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Yifan Zhang authored
GPA mode should be disabled in direct load. Signed-off-by:
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Yifan Zhang authored
Enable vcn/jpeg 4_0_2. Signed-off-by:
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Yang Wang authored
issue calltrace: [ 402.773695] [drm] failed to load ucode SMC(0x2C) [ 402.773754] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0x0) [ 402.773762] [drm:psp_load_smu_fw [amdgpu]] *ERROR* PSP load smu failed! [ 402.966758] [drm:psp_v13_0_ring_destroy [amdgpu]] *ERROR* Fail to stop psp ring [ 402.966949] [drm:psp_hw_init [amdgpu]] *ERROR* PSP firmware loading failed [ 402.967116] [drm:amdgpu_device_fw_loading [amdgpu]] *ERROR* hw_init of IP block <psp> failed -22 [ 402.967252] amdgpu 0000:03:00.0: amdgpu: amdgpu_device_ip_init failed [ 402.967255] amdgpu 0000:03:00.0: amdgpu: Fatal error during GPU init if not reset mp1 state during kernel driver unload, it will cause psp load pmfw fail at the second time. add PPSMC_MSG_PrepareMp1ForUnload support for smu_v13_0_0/smu_v13_0_7 Signed-off-by:
Yang Wang <KevinYang.Wang@amd.com> Reviewed-by:
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- 10 Jun, 2022 3 commits
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Kenneth Feng authored
support BAMACO reset on smu_v13_0_7, take BAMACO as a subset of BACO for the low latency, and it only happens on specific platforms. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Kenneth Feng authored
enable gfxoff on smu_v13_0_7 Signed-off-by:
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Kenneth Feng authored
update the driver if header for smu_v13_0_7 Signed-off-by:
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