- 02 Dec, 2016 10 commits
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Roi Dayan authored
Handling flow encap entry should be inside tc del flow and is only relevant for offloaded eswitch TC rules. Fixes: 11a457e9b6c1 ("net/mlx5e: Add basic TC tunnel set action for SRIOV offloads") Signed-off-by:Roi Dayan <roid@mellanox.com> Reviewed-by:
Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by:
Saeed Mahameed <saeedm@mellanox.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Roi Dayan authored
Change the function that deletes offloaded TC rule to get struct mlx5e_tc_flow instance which contains both the flow handle and flow attributes. This is a cleanup needed for downstream patches, it doesn't change any functionality. Signed-off-by:
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Roi Dayan authored
According to the reverse unwinding principle, on delete time we should first handle deletion of the steering rule and later handle the vlan deletion from the eswitch. Fixes: 8b32580d ("net/mlx5e: Add TC vlan action for SRIOV offloads") Signed-off-by:
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Roi Dayan authored
We will never find a flow with the same cookie as cls_flower always allocates a new flow and the cookie is the allocated memory address. Fixes: e3a2b7ed ("net/mlx5e: Support offload cls_flower with drop action") Signed-off-by:
Hadar Hen Zion <hadarh@mellanox.com> Signed-off-by:
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Tariq Toukan authored
In Striding RQ implementation, we used a single UMR (User-Mode Memory Registration) memory key for all RQs. When the product of RQs number*size gets high, we hit a limitation of u16 field size in FW. Here we move to using a UMR memory key per RQ, so we can scale to any number of rings, with the maximum buffer size in each. Signed-off-by:
Tariq Toukan <tariqt@mellanox.com> Signed-off-by:
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Tariq Toukan authored
In next patch we are going to create a UMR MKey per RQ, we need mlx5e_create_umr_mkey declared before mlx5e_create_rq. Signed-off-by:
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Tariq Toukan authored
Add new type of struct mlx5_frag_buf which is used to allocate fragmented buffers rather than contiguous, and make the Completion Queues (CQs) use it as they are big (default of 2MB per CQ in Striding RQ). This fixes the failures of type: "mlx5e_open_locked: mlx5e_open_channels failed, -12" due to dma_zalloc_coherent insufficient contiguous coherent memory to satisfy the driver's request when the user tries to setup more or larger rings. Signed-off-by:
Sebastian Ott <sebott@linux.vnet.ibm.com> Signed-off-by:
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David S. Miller authored
Neill Whillans says: ==================== net: Add support for SGMII PCS on Altera TSE MAC These patches were created as part of work to add support for SGMII PCS functionality to the Altera TSE MAC. Patches are based on 4.9-rc6 git tree. The first patch in the series adds support for the VSC8572 dual-port Gigabit Ethernet transceiver, used in integration testing. The second patch adds support for the SGMII PCS functionality to the Altera TSE driver. ==================== Signed-off-by: -
Neill Whillans authored
Add support for the (optional) SGMII PCS functionality of the Altera TSE MAC. If the phy-mode is set to 'sgmii' then we attempt to discover and initialise the PCS so that the MAC can communicate to the PHY. The PCS IP block provides a scratch register for testing presence of the PCS, which is mapped into one of the two MDIO spaces present in the MAC's register space. Once we have determined that the scratch register is functioning, we attempt to initialise the PCS to auto-negotiate an SGMII link with the PHY. There is no need to monitor or manage the SGMII link beyond this, since the normal PHY MDIO will then be used to monitor the media layer. The Altera TSE MAC has only one way in which it can be configured with an SGMII PCS, and as such, this patch only looks to the phy-mode to select whether or not to attempt to initialise the PCS registers. During initialisation, we report the PCS's equivalent of a PHY ID register. This can be parameterised during the IP instantiation and is often left as '0x00000000' which is not an error. Signed-off-by:
Neill Whillans <neill.whillans@codethink.co.uk> Reviewed-by:
Daniel Silverstone <daniel.silverstone@codethink.co.uk> Signed-off-by:
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Stephen Agate authored
Add support for the Vitesse VSC8572 which is functionally equivalent to the already supported VSC8574. As such, all the same handling functions are used since the VSC8572 merely has half the number of phy blocks internally. Signed-off-by:
Stephen Agate <stephen.agate@uk.thalesgroup.com> Signed-off-by:
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- 01 Dec, 2016 11 commits
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David S. Miller authored
Edward Cree says: ==================== sfc: defalconisation fixups A bug fix, the Kconfig change, and cleaning up a bit more unused code. ==================== Signed-off-by: -
Edward Cree authored
It's no longer used now that Falcon is gone. Also remove a reference in a comment to an ioctl that doesn't exist. Signed-off-by:
Edward Cree <ecree@solarflare.com> Signed-off-by:
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Edward Cree authored
Easy enough for Falcon users to enable it when making oldconfig. Signed-off-by:
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Edward Cree authored
Defalconisation removed one of the string arguments, but missed the corresponding %s. Fixes: 5a6681e2 ("sfc: separate out SFC4000 ("Falcon") support into new sfc-falcon driver") Signed-off-by:
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Zhang Shengju authored
Before this patch, function ndo_dflt_fdb_dump() will always return code from uc fdb dump. The reture code of mc fdb dump is lost. Signed-off-by:
Zhang Shengju <zhangshengju@cmss.chinamobile.com> Signed-off-by:
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WANG Cong authored
netlink kernel socket is protected by refcount, not RCU. Its rcv path is neither protected by RCU. So the synchronize_net() is just pointless. Cc: Richard Guy Briggs <rgb@redhat.com> Signed-off-by:
Cong Wang <xiyou.wangcong@gmail.com> Signed-off-by:
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David S. Miller authored
Raju Lakkaraju says: ==================== Adding PHY MDI(X) support I updated all review comments which were given by Andrew and Florian. This series add support for PHY MDI(X), and implement it for MSCC phys. Tested on Beaglebone Black with VSC 8531 PHY. Change set: v1: - Initial patch submit the WoL and MDI-X in single set of patches v2: - Split the mdi(x) as signal set of patches. - Remove the out_unlock as suggested by Andrew. - Add mdix_ctrl parameter in "phy_device" to handle the user configure mdi(x). Proposed implementation accepted by Florian. - phydev->mdix_ctrl initialize with ETH_TP_MDI_AUTO. Ethernet controller never initialize this parameter. - Fix the mdix changes in marvell and microchip driver. ==================== Signed-off-by: -
Raju Lakkaraju authored
PHY drivers to have an eth_tp_mdix_ctrl to indicate what is the configured MDI setting, and read eth_tp_mdi to indicate what is the current status, Add new parameter mdix_ctrl in phy_device structure and fix driver. Signed-off-by:
Raju Lakkaraju <Raju.Lakkaraju@microsemi.com> Signed-off-by:
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Raju Lakkaraju authored
To connect two ports of the same configuration (MDI to MDI or MDI-X to MDI-X) with a 10/100/1000 Mbit/s connection, an Ethernet crossover cable is needed to cross over the transmit and receive signals in the cable, so that they are matched at the connector level. When connecting an MDI port to an MDI-X port a straight through cable is used while to connect two MDI ports or two MDI-X ports a crossover cable must be used. Conventionally MDI is used on end devices while MDI-X is used on hubs and switches Auto MDI-X automatically detects the required cable connection type and configures the connection appropriately, removing the need for crossover cables to interconnect switches or connecting PCs peer-to-peer. Signed-off-by:
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Raju Lakkaraju authored
Update the mdix and mdix_ctrl with corresponding ethtool configuration parameters. Signed-off-by:
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Raju Lakkaraju authored
Add new parameter mdix_ctrl to hold the user configuration. Existing mdix maintain the current status of MDI(X) crossover performed or not. mdix_ctrl can configure either ETH_TP_MDI or ETH_TP_MDI_X orETH_TP_MDI_AUTO. Signed-off-by:
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- 30 Nov, 2016 19 commits
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Gao Feng authored
The mtu_adj is initialized to zero when alloc mem, there is no any assignment to mtu_adj. It is only used in ipvlan_adjust_mtu as one right value. So it is useless member of struct ipvl_dev, then remove it. Signed-off-by:
Gao Feng <fgao@ikuai8.com> Signed-off-by:
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Souptick Joarder authored
In alloc_cmd_box(), pci_pool_alloc() followed by memset will be replaced by pci_pool_zalloc() Signed-off-by:
Souptick joarder <jrdr.linux@gmail.com> Signed-off-by:
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Souptick Joarder authored
In mlx4_alloc_cmd_mailbox(), pci_pool_alloc() followed by memset will be replaced by pci_pool_zalloc() Signed-off-by:
Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by:
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Lorenzo Colitti authored
Commit e2d118a1 ("net: inet: Support UID-based routing in IP protocols.") made __build_flow_key call sock_net(sk) to determine the network namespace of the passed-in socket. This crashes if sk is NULL. Fix this by getting the network namespace from the skb instead. Fixes: e2d118a1 ("net: inet: Support UID-based routing in IP protocols.") Reported-by:
Erez Shitrit <erezsh@dev.mellanox.co.il> Signed-off-by:
Lorenzo Colitti <lorenzo@google.com> Signed-off-by:
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Josef Bacik authored
This is a test to verify that bpf: fix states equal logic for varlen access actually fixed the problem. The problem was if the register we added to our map register was UNKNOWN in both the false and true branches and the only thing that changed was the range then we'd incorrectly assume that the true branch was valid, which it really wasnt. This tests this case and properly fails without my fix in place and passes with it in place. Signed-off-by:
Josef Bacik <jbacik@fb.com> Acked-by:
Alexei Starovoitov <ast@kernel.org> Acked-by:
Daniel Borkmann <daniel@iogearbox.net> Signed-off-by:
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David S. Miller authored
Ivan Khoronzhuk says: ==================== cpsw: add per channel shaper configuration This series is intended to allow user to set rate for per channel shapers at cpdma level. This patchset doesn't have impact on performance. The rate can be set with: echo 100 > /sys/class/net/ethX/queues/tx-0/tx_maxrate Tested on am572xx Based on net-next/master ==================== Signed-off-by: -
Ivan Khoronzhuk authored
Split device budget between channels according to channel rate. Signed-off-by:
Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org> Signed-off-by:
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Ivan Khoronzhuk authored
Check budget fullness only after it's updated and update channel mask only once to keep budget balance between channels. It's also needed for farther changes. Signed-off-by:
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Ivan Khoronzhuk authored
This patch allows to rate limit queues tx queues for cpsw interface. The rate is set in absolute Mb/s units and cannot be more a speed an interface is connected with. The rate for a tx queue can be tested with: ethtool -L eth0 rx 4 tx 4 echo 100 > /sys/class/net/eth0/queues/tx-0/tx_maxrate echo 200 > /sys/class/net/eth0/queues/tx-1/tx_maxrate echo 50 > /sys/class/net/eth0/queues/tx-2/tx_maxrate echo 30 > /sys/class/net/eth0/queues/tx-3/tx_maxrate tc qdisc add dev eth0 root handle 1: multiq tc filter add dev eth0 parent 1: protocol ip prio 1 u32 match ip\ dport 5001 0xffff action skbedit queue_mapping 0 tc filter add dev eth0 parent 1: protocol ip prio 1 u32 match ip\ dport 5002 0xffff action skbedit queue_mapping 1 tc filter add dev eth0 parent 1: protocol ip prio 1 u32 match ip\ dport 5003 0xffff action skbedit queue_mapping 2 tc filter add dev eth0 parent 1: protocol ip prio 1 u32 match ip\ dport 5004 0xffff action skbedit queue_mapping 3 iperf -c 192.168.2.1 -b 110M -p 5001 -f m -t 60 iperf -c 192.168.2.1 -b 215M -p 5002 -f m -t 60 iperf -c 192.168.2.1 -b 55M -p 5003 -f m -t 60 iperf -c 192.168.2.1 -b 32M -p 5004 -f m -t 60 Signed-off-by:
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Ivan Khoronzhuk authored
The cpdma has 8 rate limited tx channels. This patch adds ability for cpdma driver to use 8 tx h/w shapers. If at least one channel is not rate limited then it must have higher number, this is because the rate limited channels have to have higher priority then not rate limited channels. The channel priority is set in low-hi direction already, so that when a new channel is added with ethtool and it doesn't have rate yet, it cannot affect on rate limited channels. It can be useful for TSN streams and just in cases when h/w rate limited channels are needed. Signed-off-by:
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Ivan Khoronzhuk authored
The weight of a channel is needed to split descriptors between channels. The weight can depend on maximum rate of channels, maximum rate of an interface or other reasons. The channel weight is in percentage and is independent for rx and tx channels. Signed-off-by:
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David S. Miller authored
Yuval Mintz says: ==================== qed*: Add XDP support This patch series is intended to add XDP to the qede driver, although it contains quite a bit of cleanups, refactorings and infrastructure changes as well. The content of this series can be roughly divided into: - Datapath improvements - mostly focused on having the datapath utilize parameters which can be more tightly contained in cachelines. Patches #1, #2, #8, #9 belong to this group. - Refactoring - done mostly in favour of XDP. Patches #3, #4, #5, #9. - Infrastructure changes - done in favour of XDP. Paches #6 and #7 belong to this category [#7 being by far the biggest patch in the series]. - Actual XDP support - last two patches [#10, #11]. ==================== Signed-off-by: -
Mintz, Yuval authored
Add support for forwarding via XDP. Once the eBPF is attached, driver would allocate & configure a designated transmission queue meant solely for forwarding packets. Said queue would share the receive-queue's interrupt line, and would have it's own Tx statistics. Infrastructure changes required for this [spread-out through the code]: - Determine the DMA direction of the receive buffers based on the presence of the eBPF program. - Turn the sw Tx ring into a union, as regular/XDP queues have different needs for releasing resources after completion [regular requires the SKB, XDP requires the transmitted page]. Signed-off-by:
Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by:
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Mintz, Yuval authored
Add support for the ndo_xdp callback. This patch would support XDP_PASS, XDP_DROP and XDP_ABORTED commands. This also adds a per Rx queue statistic which counts number of packets which didn't reach the stack [due to XDP]. Signed-off-by:
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Mintz, Yuval authored
Improve the cacheline usage of both queues by reordering - This reduces the cachelines required for egress datapath processing from 3 to 2 and those required by ingress datapath processing by 2. It also changes a couple of datapath related functions that currently require either the fastpath or the qede_dev, changing them to be based on the tx/rx queue instead. Signed-off-by:
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Mintz, Yuval authored
Receive-hashing is a fixed feature, so there's no need to check during the ingress datapath whether it's set or not. Signed-off-by:
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Mintz, Yuval authored
The driver needs to maintain several FW/HW-indices for each one of its queues. Currently, that mapping is done by the QED where it uses an rx/tx array of so-called hw-cids, populating them whenever a new queue is opened and clearing them upon destruction of said queues. This maintenance is far from ideal - there's no real reason why QED needs to maintain such a data-structure. It becomes even worse when considering the fact that the PF's queues and its child VFs' queues are all mapped into the same data-structure. As a by-product, the set of parameters an interface needs to supply for queue APIs is non-trivial, and some of the variables in the API structures have different meaning depending on their exact place in the configuration flow. This patch re-organizes the way L2 queues are configured and maintained. In short: - Required parameters for queue init are now well-defined. - Qed would allocate a queue-cid based on parameters. Upon initialization success, it would return a handle to caller. - Queue-handle would be maintained by entity requesting queue-init, not necessarily qed. - All further queue-APIs [update, destroy] would use the opaque handle as reference for the queue instead of various indices. The possible owners of such handles: - PF queues [qede] - complete handles based on provided configuration. - VF queues [qede] - fw-context-less handles, containing only relative information; Only the PF-side would need the absolute indices for configuration, so they're omitted here. - VF queues [qed, PF-side] - complete handles based on VF initialization. Signed-off-by: -
Mintz, Yuval authored
As qede utilizes an internal-reload sequence as result of various configuration changes, the netif state wouldn't always accurately describe the status of the configuration. To compensate, we're storing an internal state of the device, which should only be accessed under the qede_lock. This patch fixes and improves several state/lock interactions: - The internal state should only be checked while locked. - While holding lock, it's preferable to check state rather than the netdevice's state. - The reload sequence is not 'atomic' - unload and subsequent load are not in the same critical section. This also add the 'locked' variant for the reload, which would later be used by XDP - useful in the case where the correct sequence is 'lock, check state and re-configure if good', instead of allowing the reload itself to make the decision regarding the configurability of the device. Signed-off-by: -
Mintz, Yuval authored
Driver's NAPI poll is using a long sequence for processing ingress packets, and it's going to get even longer once we do XDP. Break down the main loop into a series of sub-functions to allow better readability of the function. While we're at it, correct the accounting of the NAPI budget - currently we're counting only packets passed to the stack against the budget, even in case those are actually aggregations. After refactoring every CQE processed would be counted against the budget. Signed-off-by:
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