- 25 Jan, 2019 40 commits
-
-
Josip Pavic authored
[Why] Improved contrast in ABM 2.2 is desired [How] Increase the contrast factor for ABM levels 2, 3 and 4 Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Krunoslav Kovac authored
[Why] Our output TF calculation doesn't work if no user-specified gamma correction. Normally, user provides this, but driver sohuld just assume default (linear) gamma otherwise. [How] Remove output TF dependency on user gamma being provided. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com> Signed-off-by:
-
John Barberiz authored
[Why] An uninitialized variable would randomly initialize to a large value. This caused enough delay to fail DP Compliance Test 400.2.1. [How] Initialize the variable. Signed-off-by:
John Barberiz <John.Barberiz@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
-
Josip Pavic authored
[Why] Need method of detecting which version of the DMCU FW is loaded and load the appropriate iRAM. [How] Create definition for ABM 2.2 iRAM, and load it if the DMCU FW version number matches the ABM 2.2 version; otherwise load ABM 2.1 iRAM. Signed-off-by:
-
Josip Pavic authored
[Why] Current date based versioning doesn't tell us about feature version and build version, and is not useful for debug. [How] Add versioning based on feature and build Signed-off-by:
-
David Francis authored
[Why] We were assuming that any commit with allow_modeset == false was a pageflip. This was against drm intention and only worked by sheer luck [How] A pageflip is the change from one framebuffer to another Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
-
David Francis authored
[Why] Our old logic: if pageflip, update freesync and plane address. Otherwise, update everything. This over-updated on non-pageflip cases, and it failed to update if pageflip and non-pageflip changes occurred on the same commit [How] Update flip_addrs on pageflips. Update scaling_info when it changes. Update color fields on color changes. Updates plane_info always because we don't have a good way of knowing when it needs to be updated. Unfortunately, this means that every stream commit involves two calls into DC. In particular, on pageflips there is a second, pointless update that changes nothing but costs several microseconds (about a 50% increase in time taken). The update is fast, but there are comparisons and some useless programming. Leave TODOs indicating dissatisfaction. Signed-off-by:
-
David Francis authored
[Why] amdgpu_dm_commit_planes was performing multi-plane flips incorrectly: It waited for vblank once per flipped plane It prepared flip ISR and acquired the corresponding vblank ref once per plane, although it closed ISR and put the ref once per crtc It called into dc once per flipped plane, duplicating some work [How] Wait for vblank, get vblank ref, prepare flip ISR, and call into DC only once, and only if there is a pageflip Make freesync continue to update planes even if vrr information has already been changed Signed-off-by:
-
David Francis authored
[Why] Underscan and ABM are connector properties but require updates to DC stream state. Previously, on updates to these properties the affected stream and all its planes were committed. This is unnecessary; only a few fields on the stream need to be changed. [How] If scaling or ABM have changed, change the stream and create a stream update with those changes. Call DC with only those fields. Signed-off-by:
-
David Francis authored
[Why] DC was assuming that any surface_update->scaling_info meant the update was at least medium. However, if nothing has changed there is no scaling to program, so there is no problem with the update being fast [How] If every update flag is not set, the update is fast Signed-off-by:
-
Eryk Brol authored
Virtual memory allows display to support flipping to surfaces which are not allocated contiguously in memory with physical addresses, instead a 1-4 level page table is used. This is beneficial because it allows the scattering of large surfaces to improve memory efficiency and security. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
-
Eryk Brol authored
[Why] Change DCN10 hubbub to use hubbub as a base and allow all future DCN hubbubs to do the same instead of using DCN10_hubbub. This increases readability and doesn't require future hubbubs to inherit anything other than the base hubbub struct. [How] Create separate DCN10_hubbub struct which uses the hubbub struct as a base. Signed-off-by:
-
hersen wu authored
[Why] For fastboot, Bios will light up eDP before SW driver is loaded. SW driver will check if eDP is lit by bios through reading the BIOS_SCRATCH_3 register. If lit, SW driver will not power down eDP power and phy to save time. Definition of BIOS_SCRATCH_3 are missing for pre-raven asic. This causes eDP fast boot to not work property. For some eDP panels, even if dp tx sends NoVideoStream_flag =1 and dpcd 0x600=2, eDP rx may not handle properly. This may cause a short flash on screen. [How] Add definition of BIOS_SCRATCH_3 for all asic Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Yongqiang Sun <yongqiang.sun@amd.com> Signed-off-by:
-
Andrey Grodzovsky authored
Expedite job deletion from ring mirror list to the HW fence signal callback instead from finish_work, together with waiting for all such fences to signal in drm_sched_stop we garantee that already signaled job will not be processed twice. Remove the sched finish fence callback and just submit finish_work directly from the HW fence callback. v2: Fix comments. v3: Attach hw fence cb to sched_job v5: Rebase Suggested-by:
Christian Koenig <Christian.Koenig@amd.com> Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
-
Andrey Grodzovsky authored
Decauple sched threads stop and start and ring mirror list handling from the policy of what to do about the guilty jobs. When stoppping the sched thread and detaching sched fences from non signaled HW fenes wait for all signaled HW fences to complete before rerunning the jobs. v2: Fix resubmission of guilty job into HW after refactoring. v4: Full restart for all the jobs, not only from guilty ring. Extract karma increase into standalone function. v5: Rework waiting for signaled jobs without relying on the job struct itself as those might already be freed for non 'guilty' job's schedulers. Expose karma increase to drivers. v6: Use list_for_each_entry_safe_continue and drm_sched_process_job in case fence already signaled. Call drm_sched_increase_karma only once for amdgpu and add documentation. v7: Wait only for the latest job's fence. Suggested-by:
-
Evan Quan authored
For those SKUs which support this feature only. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
-
Evan Quan authored
MGPU fan boost related parameter is added. Signed-off-by:
-
Alex Deucher authored
The power smu7 powerplay code is much more robust and has been the default for a while now. Remove the old code. Acked-by:
-
Alex Deucher authored
Check if the device is root rather before attempting to see what speeds the pcie port supports. Fixes a crash with pci passthrough in a VM. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109366Reviewed-by:
-
Alex Deucher authored
Add missing power_average to visible check for power attributes for APUs. Was missed before. Reviewed-by:
-
Evan Quan authored
As the gfxclk for SMU11 can have at most 16 discrete levels. Signed-off-by:
-
Evan Quan authored
BTC is needed before enabling all SMU features. Signed-off-by:
-
Evan Quan authored
The SOC clock needs also to fit the new performance level. Signed-off-by:
-
Evan Quan authored
No display related settings are needed on dpm level change. Signed-off-by:
-
Evan Quan authored
No dpm level setting is needed when the request level is actually same as current. Signed-off-by:
-
Jack Xiao authored
Replace the last bool type parameter with a general flags parameter, to make the last parameter be able to contain more information. v2: drop setting need_ctx_switch = false Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
-
Kenneth Feng authored
gfxclk for OD setting is limited to 1980M for non-acg ASICs of Vega10 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
-
wentalou authored
sriov would meet guest driver load failure, if calling amdgpu_asic_reset in amdgpu_device_init. sriov should skip asic_reset in device_init. Signed-off-by:
Wentao Lou <Wentao.Lou@amd.com> Acked-by:
-
Alex Deucher authored
Needs ATPX rather than _PR3 for dGPU power control. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=202263Reviewed-by:
Jim Qu <Jim.Qu@amd.com> Signed-off-by:
-
Evan Quan authored
Fix the APU judgement to make it really work as expected. Signed-off-by:
-
Evan Quan authored
So that we do not need to check this in every internal function. Signed-off-by:
-
Gustavo A. R. Silva authored
Replace kzalloc() function with its 2-factor argument form, kcalloc(). This patch replaces cases of: kzalloc(a * b, gfp) with: kcalloc(a, b, gfp) Also, improve the coding style and the use of sizeof during allocation by changing sizeof(struct dc_surface_update) and sizeof(struct dc_plane_state) to sizeof(*updates) and sizeof(*surfaces), correspondingly. This code was detected with the help of Coccinelle. Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
-
Christian König authored
This finally enables processing of ring 1 & 2. v2: fix copy&paste error Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
-
Christian König authored
Previously we only added the ring buffer memory, now add the handling as well. Signed-off-by:
-
Christian König authored
The entries are ignored for now, but it at least stops crashing the hardware when somebody tries to push something to the other IH rings. v2: limit ring size, add TODO comment v3: only program rings if they are actually allocated v4: limit the ring init to Vega10 Signed-off-by:
-
Christian König authored
Otherwise we run into a non-retry fault on access. It seems to be a hardware bug that the executable bit has higher priority than the valid bit. v2: handle clears as well Signed-off-by:
-
Christian König authored
Move the BO on the LRU only when it is actually moved by a DMA operation. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Tested-And-Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
-
Evan Quan authored
User can use "pp_dpm_dcefclk" to retrieve and adjust dcefclock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by:
-
Evan Quan authored
User can use "pp_dpm_fclk" to retrieve and adjust fclock power levels. V2: expose this interface for Vega20 and later ASICs only Signed-off-by:
-
Evan Quan authored
User can use "pp_dpm_socclk" to retrieve and adjust SOC clock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by:
-
