- 31 Aug, 2017 7 commits
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Andrew Jeffery authored
Yong Li found that writes to the AST2500 strapping register were not properly supported by the Aspeed pinctrl core and provided a patch to rectify the problem. Several revisions of the patch were posted and ultimately v4 should have been applied, however some unfortunate liberal application of tags on my part lead to confusion between v3[1] and v4[2]. Generate the diff between v3 and v4 to apply as a fixup patch. [1] http://patchwork.ozlabs.org/patch/801662/ [2] http://patchwork.ozlabs.org/patch/802946/ Cc: Yong Li <sdliyong@gmail.com> Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Dan Carpenter authored
The rza1_pctl->ports[] array has RZA1_NPORTS (12) elements. The > here should be >= to prevent an out of bounds access. Fixes: 5a49b644 ("pinctrl: Renesas RZ/A1 pin and gpio controller") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Jacopo Mondi <jacopo@jmondi.org> Signed-off-by:
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Vinay Simha BN authored
Add support for general purpose (GP) clocks for apq8064 DT binding documentation updated for qcom,apq8064-pinctrl general purpose (GP) clocks. Signed-off-by:
Vinay Simha BN <simhavcs@gmail.com> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Baolin Wang authored
This patch adds the pin control driver for Spreadtrum SC9860 platform. Signed-off-by:
Baolin Wang <baolin.wang@spreadtrum.com> Signed-off-by:
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Baolin Wang authored
This patch adds the binding documentation for Spreadtrum SC9860 pin controller device. Signed-off-by:
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Baolin Wang authored
In some scenarios, we should set some pins as input/output/pullup/pulldown when the specified system goes into deep sleep mode, then when the system goes into deep sleep mode, these pins will be set automatically by hardware. That means some pins are not controlled by any specific driver in the OS, but need to be controlled when entering sleep mode. Thus we introduce one sleep state config into pinconf-generic for users to configure. Signed-off-by:
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Ryder Lee authored
MT2701 shares the same driver with MT7623, but there is a slight difference between their pin functions (e.g., PCIe), so we update the different parts in pinmux table. Doing so, SoC could choose the correct mux setting via their own pinfun.h. Signed-off-by:
Ryder Lee <ryder.lee@mediatek.com> Cc: Biao Huang <biao.huang@mediatek.com> Signed-off-by:
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- 22 Aug, 2017 25 commits
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Mika Westerberg authored
Intel Lewisburg has the same GPIO hardware than Intel Sunrisepoint-H except few differences in register offsets and pin lists. Because of this we add a separate pinctrl driver for Lewisburg. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Mika Westerberg authored
This is desktop version Intel Cannon Lake PCH. The GPIO hardware is the same but pin list differs a bit. Add support for this to the existing Cannon Lake pin controller driver. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.14 - Propagate errors on group config, now r8a7740-armadillo800eva.dts is fixed, - Add MSIOF and USB2.0 pin groups on R-Car H3 ES2.0, - Add USB2.0 and USB3.0 pin groups on R-Car M3-W, - Add a missing MMC pin group on R-Car M2-W and RZ/G1M, - Add initial support for R-Car D3, - Small fixes and cleanups.
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Yong Li authored
On AST2500, the hardware strap register(SCU70) only accepts write ‘1’, to clear it to ‘0’, must set bits(write ‘1’) to SCU7C Signed-off-by:
Yong Li <sdliyong@gmail.com> Reviewed-by:
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Icenowy Zheng authored
The pin controller of Allwinner H5 has three IRQ banks, however in old versions of drivers and device trees, only two are set, which makes PG bank IRQ not available. If it's directly set to 3, the old device trees will fail to boot. Add a workaround (and a warning) for older device trees, and allow new device trees to use correct 3 IRQ banks. Fixes: 838adb57 ("drivers: pinctrl: add driver for Allwinner H5 SoC") Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Rushikesh S Kadam authored
The fix prevents unintended wakes from second level GPIO pin interrupts. On some Intel Kabylake platforms, it is observed that GPIO pin interrupts can wake the platform from suspend-to-idle, even though the IRQ is not configured as IRQF_NO_SUSPEND or enable_irq_wake(). This can cause undesired wakes on Mobile devices such as Laptops and Chromebook devices. For example a headset jack insertion is not a desired wake source on Chromebook devices. The pinctrl-intel (GPIO controller) driver implements a "Shared IRQ" model. All GPIO pin interrupts are OR'ed and mapped to a first level IRQ14 (or IRQ15). The driver registers an irq_chip struct and maps an irq_domain for the GPIO pin interrupts. The IRQ14 handler demuxes and calls the second level IRQ for the respective pin. In the suspend entry flow, at suspend_noirq stage, the kernel disables IRQs that are not marked for wake. The pinctrl-intel driver does not implement a irq_disable() callback (to take advantage of lazy disabling). The pinctrl-intel GPIO interrupts are not disabled in hardware during suspend entry, and thus are able to wake the SoC out of suspend-to-idle. This patch sets the IRQCHIP_MASK_ON_SUSPEND flag for the GPIO irq_chip, to disable the second level interrupts at suspend_noirq stage via the irq_mask callbacks. The irq_mask callback disables the IRQs in hardware by programming the corresponding GPIO pad registers. Only IRQs that are not marked for wake are disabled. Signed-off-by:
Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Acked-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-and-tested-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops and pctlops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
This pinmux_ops structure is only stored in the const pmxops field of a pinctrl_desc structure. Make the pinmux_ops structure const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
This pinmux_ops structure is only stored in the const pmxops field of a pinctrl_desc structure. Make the pinmux_ops structure const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
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Julia Lawall authored
This pinconf_ops structure is only stored in the const pinconf_ops field of a pinctrl_desc structure. Make the pinconf_ops structure const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
This pinctrl_ops structure is only stored in the const pctlops field of a pinctrl_desc structure. Make the pinctrl_ops structure const as well. Done with the help of Coccinelle. Signed-off-by:
Lars Persson <lars.persson@axis.com> Signed-off-by:
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Julia Lawall authored
This pinconf_ops structure is only stored in the const confops field of a pinctrl_desc structure. Make the pinconf_ops structure const as well. Done with the help of Coccinelle. Signed-off-by:
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Katsuhiro Suzuki authored
The UniPhier LD11/20 SoC audio core use following 8 pins: AO1IEC, AO1ARC, AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2] Signed-off-by:
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Gustavo A. R. Silva authored
platform_get_irq() returns an error code, but the pinctrl-amd driver ignores it and always returns -EINVAL. This is not correct and, prevents -EPROBE_DEFER from being propagated properly. Print and propagate the return value of platform_get_irq on failure. This issue was detected with the help of Coccinelle. Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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- 18 Aug, 2017 1 commit
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Linus Walleij authored
This patch: - Adds myself as comaintainer for the Gemini. - Adds the Gemini main bindings to the file list. - Adds the pin controller plus bindings to the Gemini file list. - Fixes up the path of the RTC binding and driver. Acked-by:
Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by:
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- 16 Aug, 2017 7 commits
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Takeshi Kihara authored
Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
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Takeshi Kihara authored
Signed-off-by:
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Takeshi Kihara authored
Signed-off-by:
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Takeshi Kihara authored
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77995 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds initial pinctrl driver to support for the R8A77995 SoC. Signed-off-by:
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Yoshihiro Shimoda authored
This follows the style of existion PORT_GP_X macros and will be used by a follow-up patch for the r8a77995 SoC. Extracted from the initial r8a77995 patch in the BSP by Takeshi Kihara. Signed-off-by:
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Takeshi Kihara authored
This patch adds USB30 (USB3.0 host) pin, group and function to R8A7796 SoC. Signed-off-by:
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