- 07 Nov, 2019 5 commits
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Alexander Usyskin authored
The glitch detection HW (TRC) save it status information into TRC status register. Make it available to user-space via read-only sysfs file. The TRC register is availab for PCH15 gen and newer, for older platforms reading the sysfs file will fail with EOPNOTSUPP. Signed-off-by:
Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by:
Tomas Winkler <tomas.winkler@intel.com> Link: https://lore.kernel.org/r/20191107104445.19101-1-tomas.winkler@intel.comSigned-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Tomas Winkler authored
This is to allow working with mei devices embedded within another pci device, where mei device is represented as a platform child device and fw status registers are not necessarily resident in the device pci config space. Bump the copyright year to 2019 on the modified files. Signed-off-by:
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Alexander Usyskin authored
Store irq number in hw struct to by used by synchronize_irq(). This is to allow working with mei devices embedded within another pci devices, via MFD framework, where mei device is represented as a platform device. Bump the copyright year to 2019 on hw-me.c and hw-me.h Signed-off-by:
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Tomas Winkler authored
It's enough to bind mei_device with associated 'struct device' instead of actual 'struct pci_dev'. This is to allow working with mei devices embedded within another pci device, usually via MFD framework, where mei device is represented as a platform device. Bump copyright year to 2019 on effected files. Signed-off-by:
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Greg Kroah-Hartman authored
Merge tag 'phy-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into char-misc-next Kishon writes: phy: for 5.5 *) Add a new PHY driver for USB3 PHY on Allwinner H6 SoC *) Add a new PHY driver for Innosilicon Video Combo PHY(MIPI/LVDS/TTL) *) Add support in xusb-tegra210 PHY driver to get USB device mode functional in Tegra 210 *) Add support for SM8150 QMP UFS PHY in phy-qcom-qmp PHY driver *) Fix smatch warning (array off by one) in phy-rcar-gen2 PHY driver *) Enable mac tx internal delay for rgmii-rxid in phy-gmii-sel driver *) Fix phy-qcom-usb-hs from registering multiple extcon notifiers during PHY power cycle *) Use devm_platform_ioremap_resource() in phy-mvebu-a3700-utmi, phy-hisi-inno-usb2, phy-histb-combphy and regulator_bulk_set_supply_names() in xusb to simplify code *) Remove unused variable in xusb-tegra210 and phy-dm816x-usb *) Fix sparse warnings in phy-brcm-usb-init Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (28 commits) phy: phy-rockchip-inno-usb2: add phy description for px30 phy: qcom-usb-hs: Fix extcon double register after power cycle phy: renesas: phy-rcar-gen2: Fix the array off by one warning phy: lantiq: vrx200-pcie: fix error return code in ltq_vrx200_pcie_phy_power_on() dt-bindings: phy: add yaml binding for rockchip,px30-dsi-dphy phy/rockchip: Add support for Innosilicon MIPI/LVDS/TTL PHY phy: add PHY_MODE_LVDS phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC dt-bindings: Add bindings for USB3 phy on Allwinner H6 phy: qcom-qmp: Add SM8150 QMP UFS PHY support dt-bindings: phy-qcom-qmp: Add sm8150 UFS phy compatible string phy: ti: gmii-sel: fix mac tx internal delay for rgmii-rxid phy: tegra: use regulator_bulk_set_supply_names() phy: ti: dm816x: remove set but not used variable 'phy_data' phy: renesas: rcar-gen3-usb2: Fix sysfs interface of "role" phy: tegra: xusb: Add vbus override support on Tegra186 phy: tegra: xusb: Add vbus override support on Tegra210 phy: tegra: xusb: Add usb3 port fake support on Tegra210 phy: tegra: xusb: Add XUSB dual mode support on Tegra210 dt-bindings: rcar-gen3-phy-usb3: Add r8a774b1 support ...
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- 05 Nov, 2019 15 commits
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Finley Xiao authored
Newer Rockchip socs like the px30 use a different one-time-programmable memory controller for things like cpu-id and leakage information, so add the necessary driver for it. Signed-off-by:
Finley Xiao <finley.xiao@rock-chips.com> [ported from vendor 4.4, converted to clock-bulk API and cleanups] Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20191029114240.14905-11-srinivas.kandagatla@linaro.orgSigned-off-by:
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Heiko Stuebner authored
Newer Rockchip SoCs use a different IP for accessing special one- time-programmable memory, so add a binding for these controllers. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Srinivas Kandagatla authored
Fix below error by adding HAVE_ARM_SMCCC dependency in Kconfig ERROR: "__arm_smccc_smc" [drivers/nvmem/nvmem-imx-ocotp-scu.ko] undefined! Reported-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
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Freeman Liu authored
The Spreadtrum eFuse controller is widely used to dump chip ID, configuration setting, function select and so on, as well as supporting one-time programming. Signed-off-by:
Freeman Liu <freeman.liu@unisoc.com> Signed-off-by:
Baolin Wang <baolin.wang@linaro.org> Signed-off-by:
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Freeman Liu authored
This patch adds the binding documentation for Spreadtrum eFuse controller. Signed-off-by:
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Lucas Stach authored
If software running before the OCOTP driver is loaded left the controller with the error status pending, the driver will never be able to complete the read timing setup. Reset the error status on probe to make sure the controller is in usable state. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
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Peng Fan authored
The fuse programming from non-secure world is blocked, so we could only use Arm Trusted Firmware SIP call to let ATF program fuse. Because there is ECC region that could only be programmed once, so add a heler in_ecc to check the ecc region. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
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Peng Fan authored
Introduce HOLE/ECC_REGION flag and in_hole helper to ease the check of hole region. The ECC_REGION is also introduced here which is preparing for programming support. ECC_REGION could only be programmed once, so need take care. Signed-off-by:
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Baolin Wang authored
Change to use devm_hwspin_lock_request_specific() to help to simplify the cleanup code for drivers requesting one hwlock. Thus we can remove the redundant sc27xx_efuse_remove() and platform_set_drvdata(). Signed-off-by:
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Sebastian Reichel authored
nvmem_cell_write's buf argument uses different types based on the configuration of CONFIG_NVMEM. The function prototype for enabled NVMEM uses 'void *' type, but the static dummy function for disabled NVMEM uses 'const char *' instead. Fix the different behaviour by always expecting a 'void *' typed buf argument. Fixes: 7a78a7f7 ("power: reset: nvmem-reboot-mode: use NVMEM as reboot mode write interface") Reported-by:
Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-By:
Han Nandor <nandor.han@vaisala.com> Signed-off-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Acked-by:
Eli Billauer <eli.billauer@gmail.com> Link: https://lore.kernel.org/r/20191016092546.26332-1-yuehaibing@huawei.comSigned-off-by:
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Marcel Holtmann authored
udev has a feature of creating /dev/<node> device-nodes if it finds a devnode:<node> modalias. This allows for auto-loading of modules that provide the node. This requires to use a statically allocated minor number for misc character devices. However, rfkill uses dynamic minor numbers and prevents auto-loading of the module. So allocate the next static misc minor number and use it for rfkill. Signed-off-by:
Marcel Holtmann <marcel@holtmann.org> Link: https://lore.kernel.org/r/20191024174042.19851-1-marcel@holtmann.orgSigned-off-by:
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Alexander Usyskin authored
Comet Point (Comet Lake) V device id. Cc: <stable@vger.kernel.org> Signed-off-by:
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Alexander Usyskin authored
Add parent device name to the name of devices on bus to avoid device names collisions for same client UUID available from different MEI heads. Namely this prevents sysfs collision under /sys/bus/mei/device/ In the device part leave just UUID other parameters that are required for device matching are not required here and are just bloating the name. Cc: <stable@vger.kernel.org> Signed-off-by:
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Greg Kroah-Hartman authored
Merge tag 'extcon-next-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon into char-misc-next Chanwoo writes: Update extcon for 5.5 Detailed description for this pull request: 1. Clean up the and fix the minor issue of extcon provider driver - extcon-intel-cht-wc don't reset the USB data connection at probe time in order to prevent the removing all devices from bus. - extcon-sm5502 reset the registers at proble time in order to prevent the some stuck state. And remove the redundant variable initializaiton. * tag 'extcon-next-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon: extcon: sm5502: remove redundant assignment to variable cable_type extcon: sm5502: Reset registers during initialization extcon-intel-cht-wc: Don't reset USB data connection at probe
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- 04 Nov, 2019 14 commits
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Rikard Falkeborn authored
The second argument should be the lsb and the third argument should be the msb. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20191104181251.26732-15-mathieu.poirier@linaro.orgSigned-off-by:
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Yabin Cui authored
When tracing etm data of multiple threads on multiple cpus through perf interface, some link devices are shared between paths of different cpus. It creates race conditions when different cpus wants to enable/disable the same link device at the same time. Example 1: Two cpus want to enable different ports of a coresight funnel, thus calling the funnel enable operation at the same time. But the funnel enable operation isn't reentrantable. Example 2: For an enabled coresight dynamic replicator with refcnt=1, one cpu wants to disable it, while another cpu wants to enable it. Ideally we still have an enabled replicator with refcnt=1 at the end. But in reality the result is uncertain. Since coresight devices claim themselves when enabled for self-hosted usage, the race conditions above usually make the link devices not usable after many cycles. To fix the race conditions, this patch uses spinlocks to serialize enabling/disabling link devices. Fixes: a06ae860 ("coresight: add CoreSight core layer framework") Signed-off-by:
Yabin Cui <yabinc@google.com> Signed-off-by:
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Mark Brown authored
Coresight hardware is only likely to appear on Arm systems and currently the core code has Arm-specific barrier operations in it so can't be built anywhere else so add an explicit dependency saying so. This will make no practical difference currently due to the way subsystems are referenced, the subsystem is only pulled in on arm and arm64, so mainly serves as documentation in case someone wants to increase build coverage. Signed-off-by:
Mark Brown <broonie@kernel.org> Signed-off-by:
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Mike Leach authored
An API to control single-shot comparator operation was missing from sysfs. This adds the parameters to sysfs to allow programming of this feature. Signed-off-by:
Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Mike Leach authored
Currently it is not possible to view the current settings of a given address comparator without knowing what type it is set to. For example, if a comparator is set as an addr_start comparator, attempting to read addr_stop for the same index will result in an error. addr_cmp_view is added to allow the user to see the current settings of the indexed address comparator without resorting to trial and error when the set type is not known. Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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Mike Leach authored
Context ID and VM ID masks required 2 value inputs, even when the second value is ignored as insufficient CID / VMID comparators are implemented. Permit a single value to be used if that is sufficient to cover all implemented comparators. Signed-off-by:
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Mike Leach authored
Setting include / exclude on a range had to be done by setting the bit in 'mode' before setting the range. However, setting this bit also had the effect of altering the current range as well. Changed to only set include / exclude setting of a range at the point of setting that range. Either use a 3rd input parameter as the include exclude value, or if not present use the current value of 'mode'. Do not change current range when 'mode' changes. Signed-off-by:
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Mike Leach authored
Fixes the following issues when using the ETMv4 start-stop logic. 1) Setting a start or a stop address should not automatically set the start-stop status to 'on'. The value set by the user in 'mode' must be respected or start instances could be missed. 2) Missing API for controlling TRCVIPCSSCTLR - start stop control by PE comparators. 3) Default ETM configuration sets a trace all range, and correctly sets the start-stop status bit. This was not being correctly reflected in the 'mode' parameter. Signed-off-by:
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Mike Leach authored
TRCACATRn registers have match bits for secure and non-secure exception levels which are not accessible by the sysfs API. This adds a new sysfs parameter to enable this - addr_exlevel_s_ns. Signed-off-by:
Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by:
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Mike Leach authored
A number of issues are fixed relating to sysfs input validation:- 1) bb_ctrl_store() - incorrect compare of bit select field to absolute value. Reworked per ETMv4 specification. 2) seq_event_store() - incorrect mask value - register has two event values. 3) cyc_threshold_store() - must mask with max before checking min otherwise wrapped values can set illegal value below min. 4) res_ctrl_store() - update to mask off all res0 bits. Reviewed-by:
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Mike Leach authored
ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates). Patch accounts for this new capability. Signed-off-by:
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Tanmay Vilas Kumar Jagdale authored
Add ETMv4 periperhal ID for Marvell's ThunderX2 chip. This chip contains ETMv4.1 version. Signed-off-by:
Tanmay Vilas Kumar Jagdale <tanmay@marvell.com> Signed-off-by:
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Andrew Murray authored
Some coresight components, because of choices made during hardware integration, require their state to be saved and restored across CPU low power states. The software has no reliable method of detecting when save/restore is required thus let's add a binding to inform the kernel. Signed-off-by:
Andrew Murray <andrew.murray@arm.com> Reviewed-by:
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Andrew Murray authored
Some hardware will ignore bit TRCPDCR.PU which is used to signal to hardware that power should not be removed from the trace unit. Let's mitigate against this by conditionally saving and restoring the trace unit state when the CPU enters low power states. This patchset introduces a firmware property named 'arm,coresight-loses-context-with-cpu' - when this is present the hardware state will be conditionally saved and restored. A module parameter 'pm_save_enable' is also introduced which can be configured to override the firmware property. This can be set to never allow save/restore or to conditionally allow it (only for self-hosted). The default value is determined by firmware. We avoid saving the hardware state when self-hosted coresight isn't in use to reduce PM latency - we can't determine this by reading the claim tags (TRCCLAIMCLR) as these are 'trace' registers which need power and clocking, something we can't easily provide in the PM context. Therefore we rely on the existing drvdata->mode internal state that is set when self-hosted coresight is used (and powered). Signed-off-by:
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- 03 Nov, 2019 1 commit
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Johannes Thumshirn authored
Now that we have symbol namespaces, use them in MCB to not pollute the default namespace with MCB internals. Signed-off-by:
Johannes Thumshirn <jthumshirn@suse.de> Reviewed-by:
Jessica Yu <jeyu@kernel.org> Reviewed-by:
Michael Moese <mmoese@suse.de> Link: https://lore.kernel.org/r/20191016100158.1400-1-jthumshirn@suse.deSigned-off-by:
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- 31 Oct, 2019 5 commits
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Heiko Stuebner authored
The px30 soc from Rockchip shares the same register description as the rk3328, so can re-use its definitions. Signed-off-by:
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Stephan Gerhold authored
Commit f0b5c2c9 ("phy: qcom-usb-hs: Replace the extcon API") switched from extcon_register_notifier() to the resource-managed API, i.e. devm_extcon_register_notifier(). This is problematic in this case, because the extcon notifier is dynamically registered/unregistered whenever the PHY is powered on/off. The resource-managed API does not unregister the notifier until the driver is removed, so as soon as the PHY is power cycled, attempting to register the notifier again results in: double register detected WARNING: CPU: 1 PID: 182 at kernel/notifier.c:26 notifier_chain_register+0x74/0xa0 Call trace: ... extcon_register_notifier+0x74/0xb8 devm_extcon_register_notifier+0x54/0xb8 qcom_usb_hs_phy_power_on+0x1fc/0x208 ... ... and USB stops working after plugging the cable out and in another time. The easiest way to fix this is to make a partial revert of commit f0b5c2c9 ("phy: qcom-usb-hs: Replace the extcon API") and avoid using the resource-managed API in this case. Fixes: f0b5c2c9 ("phy: qcom-usb-hs: Replace the extcon API") Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Signed-off-by:
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Biju Das authored
Fix the below smatch warning by adding variable check rather than the hardcoded value. warn: array off by one? 'data->select_value[channel_num]' Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
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Wei Yongjun authored
Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: e52a6321 ("phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY") Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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Heiko Stuebner authored
This adds a yaml binding for the external dsi phy found on Rockchip socs of the px30, rk3128 and rk3368 variants. Signed-off-by:
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