- 25 Jan, 2022 40 commits
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Aric Cyr authored
This version brings along the following fixes: - Z9 improvements - Clocks management adjustments - Code cleanup - Improve DSC and MST code Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Wayne Lin authored
[Why & How] In order to easily test ilr by immediately reset the preferred training settings, fix the code to disable skip_immediate_retrain. Tested-by:
Solomon Chiu <solomon.chiu@amd.com> Acked-by:
Wayne Lin <Wayne.Lin@amd.com> Signed-off-by:
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Anthony Koo authored
- Add Scr8 for GPINT messaging between driver and fw Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Reza Amini authored
[why] OnSetSourceContentAttribute it does not trigger an update for the VSC with TF change. [how] In this call, create a new VSC infoPacket based on the new config, and allow DisplayTarget decide if an update and pursuant passive flip is necessary Tested-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Reza Amini <Reza.Amini@amd.com> Signed-off-by:
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Sung Joon Kim authored
[why] Due to bad hardware, the PHY repeater count in LTTPR cap is read as 0xFF in some monitors while the LTTPR is actually present. [how] Remove PHY repeater counter check when configuring LTTPR mode. Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Sung Joon Kim <sungkim@amd.com> Signed-off-by:
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Roy Chan authored
[Why] indirect register index/data pair may be used by multi-threads. when it happens, it would cause register access issue that is hard to trace. [How] Using cgs service, which provide a sync indirect reg access api. Tested-by:
Roy Chan <roy.chan@amd.com> Signed-off-by:
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Fangzhi Zuo authored
DSC sequence for non virtual dpcd synaptics hub Tested-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Fangzhi Zuo authored
Determine if DFP present and the type of downstream device based on dsc_aux Tested-by:
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Fangzhi Zuo authored
Sequence to reset synaptics SDP fifo before enabling first stream Tested-by:
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Shen, George authored
[Why/How] We need to handle cable capabilities for cables that support cable ID. The cable attributes are intersected with the verified link caps to determine appropriate max link rate. After determining cable attributes we update the DP receiver. Tested-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
George Shen <George.Shen@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] If the DPCD caps specifies a PSR version newer than PSR_VERSION_1 then we fallback to using PSR_VERSION_1 in amdgpu_dm_set_psr_caps. This gets overriden with the raw DPCD value in amdgpu_dm_link_setup_psr, which can result in DMCUB hanging if we pass in an unsupported PSR version number. [How] Fix the hang by using link->psr_settings.psr_version directly during amdgpu_dm_link_setup_psr. Tested-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Ian Chen authored
Prepare for future dm can have different implementation depends on the return value. Tested-by:
Ian Chen <ian.chen@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] DMCUB will hang if we send a PSR unsupported set version command. This can occur if we fall-through into the default case in the switch statement for PSR version. [How] Add an unsupported check after the switch statement. Tested-by:
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Varone authored
[WHY?] SKUs that contain an unused eDP connector will throw an error when no display is connected. [HOW?] Change error to a warning. Tested-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Dillon Varone <divarone@amd.com> Signed-off-by:
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Alvin Lee authored
Implement handling for escape call to query the MCLK switch support for the current display config. Tested-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Josip Pavic authored
[Why & How] Increase width of some variables to avoid comparing integers of different widths Tested-by:
Josip Pavic <Josip.Pavic@amd.com> Signed-off-by:
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Martin Tsai authored
[Why] Link encoders are created based on its engine ID. The position of a link encoder in an array could be null since it didn't be allocated. Current matching logic didn't consider this situation and could get null encoder. [How] To add null encoder check to make the matching logic can go to next to get a valid one. Tested-by:
Martin Tsai <martin.tsai@amd.com> Signed-off-by:
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Wayne Lin authored
[Why] Currently, when we're tentatively detecting link configuration under mst case, we will wrongly notify a none existing stream sink to drm layer. It's due to we'll call amdgpu_dm_update_connector_after_detect() within dm_helpers_read_local_edid() to update connector when we're still under tentative detection procedure. [How] dm_helpers_read_local_edid() was designed to do "read" only. Don't update drm connector status when we're still under detection process. Tested-by:
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Wenjing Liu authored
[why] There is a recent refactor that contains a typo to cause set throttled vcp size skipped for dpia link. The change is to fix this typo so it won't cause black screen Tested-by:
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Wenjing Liu authored
[why] This is internal to dc so we don't have to add a prefix to indicate it is dc link_hwss instead someone else link_hwss. Tested-by:
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Wenjing Liu authored
[why] as we add more link_hwss we are making a generic way to determine which type of link_hwss we should use. Later on we may think of introduce a link policy layer. it could be a thin layer that decide the type of link_hwss we use. So instead of passing in link and link_res we can just pass in link_policy and swtich based on link_policy->get_link_hwss_type. Tested-by:
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Wenjing Liu authored
[why] Current we have hundreds of if/else or switch statement to check encoder type in dc_link level. The reason is because depending on the type of encoder dc_link needs to perform similar programming task but with different encoder interfaces. The story is to abstract these interfaces so dc_link can just perform the programming task without knowing the detail of which encoder it's dealing with. Tested-by:
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Wenjing Liu authored
[Why & How] DCN guard is not necessary for DP2.x relevant logic. Drop them. v2: squash in fix for misplaced #endif (Alex) Tested-by:
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Jimmy Kizito authored
[Why] According to the USB4 specification, FEC and DSC should be disabled when a USB4 DPIA operates in TBT3 compatibility mode. [How] Upon detecting that a USB4 DPIA is connected to a device that is known to operate in TBT3 mode, disable FEC and DSC support if they have been reported by the TBT3 device. Tested-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Acked-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] dc_link_detect_helper has multiple purpose: 1. Detect link and local sink. 2. Verify link capability by performing detection link training. 3. Start mst topology discovery and if succeeded fails the current interface. This is difficult to maintain as item 2 has become more destructive to current dc state. The change is to decouple these sequences to its own functions. Eventually only item 2 is a destructive method and we will redesign this sequence with a more unified policy across different encoder types. Tested-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Lang Yu authored
Remove redundant code and use general smu_v11_0_fini_smc_tables function. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Lang Yu authored
Some clients(e.g., kfd) query sclk/mclk through this function. As cyan skillfish doesn't support dpm, for sclk, set min/max to CYAN_SKILLFISH_SCLK_MIN/CYAN_SKILLFISH_SCLK_MAX(to maintain the existing logic).For others, set both min and max to current value. Before this patch: # /opt/rocm/opencl/bin/clinfo Max clock frequency: 0Mhz After this patch: # /opt/rocm/opencl/bin/clinfo Max clock frequency: 2000Mhz v2: - Maintain the existing min/max sclk logic.(Lijo) v3: - Avoid fetching metrics table twice.(Lijo) Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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yipechai authored
This reverts commit df4f0041. Xgmi ras initialization had been moved from .late_init to early_init, the defect of repeated calling amdgpu_ras_register_ras_block had been fixed, so revert this patch. Signed-off-by:
yipechai <YiPeng.Chai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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yipechai authored
Move xgmi ras initialization from .late_init to .early_init, which let xgmi ras can be initialized only once. Signed-off-by:
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Stanley.Yang authored
Pmfw read ecc info registers in the following order, umc0: ch_inst 0, 1, 2 ... 7 umc1: ch_inst 0, 1, 2 ... 7 The position of the register value stored in eccinfo table is calculated according to the below formula, channel_index = umc_inst * channel_in_umc + ch_inst Driver directly use the index of eccinfo table array as channel index, it's not correct, driver needs convert eccinfo table array index to channel index according to channel_idx_tbl. Reviewed-by:Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by:
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Hawking Zhang authored
create a common helper function for soc15 and onwards to read bios image from rom Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Hawking Zhang authored
Not needed anymore. Signed-off-by:
Zhou, Peng Ju <PengJu.Zhou@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Hawking Zhang authored
Instead of ip specific implementation for rlcg indirect register access Signed-off-by:
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Hawking Zhang authored
The helper will be used to access registers from sriov guest in full access time Signed-off-by:
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Hawking Zhang authored
Initialize all the register offsets that will be used in rlcg indirect reg access path for gfx10 in sw_init phase Signed-off-by:
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Hawking Zhang authored
Initialize all the register offsets that will be used in rlcg indirect reg access path for gfx9 in sw_init phase Signed-off-by:
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Hawking Zhang authored
Add structures that are used to cache registers offsets for rlcg indirect reg access ctrl and flag availability of such interface Signed-off-by:
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Hawking Zhang authored
Switch to common helper to query rlcg access flag specified by sriov host driver for gfx10 Signed-off-by:
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Hawking Zhang authored
Switch to common helper to query rlcg access flag specified by sriov host driver for gfx9 Signed-off-by:
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Hawking Zhang authored
Query rlc indirect register access approach specified by sriov host driver per ip blocks Signed-off-by:
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