- 18 Mar, 2024 24 commits
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Abel Vesa authored
The X1E80100 platform implements the v7 SPMI arbiter, which means it implements two separate buses. The difference, when compared to existing platforms that also implement v7 SPMI arbiter, is that this is the first platform that actually has boards with secondary bus populated with some PMICs. This is why it needs to have 2 separate buses as child nodes of the arbiter. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240222-x1e80100-dts-smb2360-v3-1-85a691d4f68a@linaro.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Danila Tikhonov authored
Define VBUS regulator and the Type-C handling block as present on the Qualcomm PM6150 PMIC. Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240220202147.228911-3-danila@jiaxyga.comSigned-off-by:
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Luca Weiss authored
Add the definition for the USB-C connector found on this phone and hook up the relevant bits. This enables USB role switching. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240220-fp3-typec-v1-1-1930cad81139@fairphone.comSigned-off-by:
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Luca Weiss authored
Add crypto engine (CE) and CE BAM related nodes and definitions for this SoC. For reference: [ 2.297419] qcrypto 1dfa000.crypto: Crypto device found, version 5.5.1 Signed-off-by:
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Krishna Kurapati authored
Recent binding update [1] indicates that there are hs_phy_irq present in primary and secondary usb controllers of sc8280xp. Add the missing hs_phy_irq for these controllers. Since the driver doesn't use this interrupt, this change has been only compile tested. [1]: https://lore.kernel.org/all/20231227091951.685-2-quic_kriskura@quicinc.com/Signed-off-by:
Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240219075720.640529-1-quic_kriskura@quicinc.comSigned-off-by:
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Anton Bambura authored
The UFS driver expects to be able to set load (and by extension, mode) on the supplied regulators. Add the necessary properties to make that possible. Based on https://lore.kernel.org/r/20231214-topic-sc8180_fixes-v1-6-421904863006@linaro.orgSigned-off-by:
Anton Bambura <jenneron@postmarketos.org> Reviewed-by:
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Anton Bambura authored
This solves the issue when touchpad gets stuck on right or middle click. This also makes touchpad working smoother. Signed-off-by:
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Anton Bambura authored
Split keyboard and touchpad pinctrl nodes since they are for different devices and move keyboard, touchpad and touchscreen pinctrl references to appropriate nodes. Signed-off-by:
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Anton Bambura authored
Set names, so they correspond to devices connected to these interfaces. Signed-off-by:
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Anton Bambura authored
Fix GPU firmware path so it uses model-specific directory. Signed-off-by:
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Richard Acayan authored
Add the panel used in the Google Pixel 3a. Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20240209001639.387374-9-mailingradian@gmail.comSigned-off-by:
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Neil Armstrong authored
By default the DSP domains are non secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: 10e02467 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-3-15c4c864310f@linaro.orgSigned-off-by:
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Neil Armstrong authored
By default the DSP domains are non secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: d0c061e3 ("arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodes") Signed-off-by:
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Neil Armstrong authored
By default the DSP domains are non secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: 91d70eb7 ("arm64: dts: qcom: sm8450: add fastrpc nodes") Signed-off-by:
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Bjorn Andersson authored
Without explicitly specifying names for the regulators they are named based on the DeviceTree node name. This results in multiple regulators with the same name, making debug prints and regulator_summary impossible to reason about. Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
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Krzysztof Kozlowski authored
Each pair of WSA8845 speakers share the powerdown SD_N GPIO, thus this GPIO is specified twice in each WSA8845 device node. Such DTS was added hoping non-exclusive GPIO usage would be accepted, but it turned out otherwise: it is not supported by the Linux kernel. Linux kernel however supports sharing reset GPIOs, when used bia the reset controller framework as implemented in commit 26c8a435 ("ASoC: dt-bindings: qcom,wsa8840: Add reset-gpios for shared line") and commit c721f189 ("reset: Instantiate reset GPIO controller for shared reset-gpios"). Convert the property with shutdown GPIO to "reset-gpios" to use mentioned Linux kernel feature. This allows to bring all four speakers out of reset. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Correct the SWR1 Soundwire controller port block pack mode to match reference code. Not sure if this has any impact. Signed-off-by:
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Loic Poulain authored
Add a node for the Limits Management Hardware to ensure it can be configured by the operating system. Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> [Konrad: add commit msg, rebase] Signed-off-by:
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Konrad Dybcio authored
To allow for swift EDL reboots, describe the respective register under the scm node. Signed-off-by:
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Konrad Dybcio authored
Killing the platform with a single write and no firmware involvement is pretty cool, add support for it. Note that due to restart notifier priority settings, PSCI reset will be used instead, unless: a) PSCI is not exposed by the firmware (e.g. because the fw was replaced) or b) PSCI restart fails for some reason Signed-off-by:
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Konrad Dybcio authored
Describe the QFPROM NVMEM block. Also, add a subnode to represent the GPU speed bin region within it. Signed-off-by:
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Jianhua Lu authored
Add usb pd negotiation, but charging is controlled by pm8150b pmic, so it can only charge battery with 5W, Signed-off-by:
Jianhua Lu <lujianhua000@gmail.com> Link: https://lore.kernel.org/r/20240302131025.13741-1-lujianhua000@gmail.comSigned-off-by:
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Johan Hovold authored
The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS). Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. Note that using the GIC ITS on SC8280XP will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. This will specifically lead to notifications about Correctable Errors being logged for the Wi-Fi controller on the Lenovo ThinkPad X13s when ASPM L0s is enabled. Suggested-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240306095651.4551-6-johan+linaro@kernel.orgSigned-off-by:
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Johan Hovold authored
Add the missing PCIe CX performance level votes to avoid relying on other drivers (e.g. USB or UFS) to maintain the nominal performance level required for Gen3 speeds. Fixes: 813e8315 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Cc: stable@vger.kernel.org # 6.2 Reviewed-by:
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- 17 Mar, 2024 2 commits
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Konrad Dybcio authored
Hook up the interrupts that signal the Limits Management Hardware has started some sort of throttling action. In testing, you may notice the A78C cluster throttle IRQ fire count stays at zero. After an hour of painful experiments on an X13s, I was able to get that cluster to heat up near 90 degC, after which the IRQ has indeed fired. So it stands to reason that the heat output difference between the A78C and X1C clusters is so massive that LMH rarely decides to throttle the "little" one based on its power metrics. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
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Ritesh Kumar authored
Enable Display Subsystem with Novatek NT36672E Panel on qcm6490 idp platform. Signed-off-by:
Ritesh Kumar <quic_riteshk@quicinc.com> Reviewed-by:
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- 04 Mar, 2024 3 commits
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Jianhua Lu authored
Xiaomi Pad 5 Pro has a 2560x1600 portrait screen, set RIGHT_UP rotation to make it look like a landscape screen. Signed-off-by:
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Abel Vesa authored
The actual size of the channels registers region is 4MB, according to the documentation. This issue was not caught until now because the driver was supposed to allow same regions being mapped multiple times for supporting multiple buses. Thie driver is using platform_get_resource_byname() and devm_ioremap() towards that purpose, which intentionally avoids devm_request_mem_region() altogether. Fixes: 10e02467 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Reviewed-by:
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Abel Vesa authored
The actual size of the channels registers region is 4MB, according to the documentation. This issue was not caught until now because the driver was supposed to allow same regions being mapped multiple times for supporting multiple buses. Thie driver is using platform_get_resource_byname() and devm_ioremap() towards that purpose, which intentionally avoids devm_request_mem_region() altogether. Fixes: ffc50b2d ("arm64: dts: qcom: Add base SM8550 dtsi") Reviewed-by:
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- 20 Feb, 2024 1 commit
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Dmitry Baryshkov authored
The patch adding Type-C support for sm6115 was misapplied. All the orientation switch configuration ended up at the UFS PHY node instead of the USB PHY node. Move the data bits to the correct place. Fixes: a06a2f12 ("arm64: dts: qcom: qrb4210-rb2: enable USB-C port handling") Signed-off-by:
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- 19 Feb, 2024 3 commits
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Manivannan Sadhasivam authored
"msi-map-mask" is a required property for all Qcom PCIe controllers as it would allow all PCIe devices under a bus to share the same MSI identifier. Without this property, each device has to use a separate MSI identifier which is not possible due to platform limitations. Currently, this is not an issue since only one device is connected to the bus on boards making use of this SoC. Fixes: a33a532b ("arm64: dts: qcom: sm8650: Use GIC-ITS for PCIe0 and PCIe1") Signed-off-by:
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Krzysztof Kozlowski authored
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20240213145124.342514-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Stefan Hansson authored
This documents Samsung Galaxy Tab 4 10.1 LTE (samsung,matisselte) which is a tablet by Samsung based on the MSM8926 SoC. Signed-off-by:
Stefan Hansson <newbyte@postmarketos.org> Reviewed-by:
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- 17 Feb, 2024 1 commit
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Dmitry Baryshkov authored
Define VBUS regulator and the Type-C handling block as present on the Quacomm PM4125 PMIC. Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240202-pm4125-typec-v2-3-12771d85700d@linaro.orgSigned-off-by:
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- 16 Feb, 2024 6 commits
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Lucas Karpinski authored
pcie2a and pcie3a both cause interrupt storms to occur. However, when both are enabled simultaneously, the two combined interrupt storms will lead to rcu stalls. Red Hat is the only company still using this board and since we still need pcie3a, just disable pcie2a. Signed-off-by:
Lucas Karpinski <lkarpins@redhat.com> Reviewed-by:
Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/r/qcoqksikfvdqxk6stezbzc7l2br37ccgqswztzqejmhrkhbrwt@ta4npsm35mqkSigned-off-by:
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Viken Dadhaniya authored
Populate the DTSI node for slimbus instance to be used by bluetooth FM audio case. Signed-off-by:
Viken Dadhaniya <quic_vdadhani@quicinc.com> Link: https://lore.kernel.org/r/20240215090910.30021-1-quic_vdadhani@quicinc.comSigned-off-by:
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Ankit Sharma authored
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn is used by EAS to take placement decisions. So add it to SC7280 soc. Signed-off-by:
Ankit Sharma <quic_anshar@quicinc.com> Reviewed-by:
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Luca Weiss authored
With SDAM + PBS the LPG driver can configure the LED pattern in hardware. Signed-off-by:
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Neil Armstrong authored
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs received from endpoint devices to the CPU using GIC-ITS MSI controller. Add support for it. The GIC-ITS MSI implementation provides an advantage over internal MSI implementation using Locality-specific Peripheral Interrupts (LPI) that would allow MSIs to be targeted for each CPU core. Like SM8450, the IDs are swapped, but works fine on PCIe0 and PCIe1. WiFi PCIe Device on SM8550-QRD using GIC-ITS: 218: 0 4 0 0 0 0 0 0 ITS-MSI 524288 Edge bhi 219: 0 0 5 0 0 0 0 0 ITS-MSI 524289 Edge mhi 220: 0 0 0 33 0 0 0 0 ITS-MSI 524290 Edge mhi 221: 0 0 0 0 3 0 0 0 ITS-MSI 524291 Edge ce0 222: 0 0 0 0 0 1 0 0 ITS-MSI 524292 Edge ce1 223: 0 0 0 0 0 0 38 0 ITS-MSI 524293 Edge ce2 224: 0 0 0 0 0 0 0 31 ITS-MSI 524294 Edge ce3 225: 0 0 0 0 0 0 0 0 ITS-MSI 524295 Edge ce5 226: 0 0 0 0 0 0 0 0 ITS-MSI 524296 Edge DP_EXT_IRQ 227: 0 0 0 0 0 0 0 0 ITS-MSI 524297 Edge DP_EXT_IRQ 228: 0 0 0 0 0 0 0 0 ITS-MSI 524298 Edge DP_EXT_IRQ 229: 0 0 0 0 0 0 0 0 ITS-MSI 524299 Edge DP_EXT_IRQ 230: 0 0 0 0 0 0 0 0 ITS-MSI 524300 Edge DP_EXT_IRQ 231: 0 0 0 0 0 0 0 0 ITS-MSI 524301 Edge DP_EXT_IRQ 232: 0 0 0 0 0 0 0 0 ITS-MSI 524302 Edge DP_EXT_IRQ NVMe in SM8550-HDK M.2 Slot using GIC-ITS: 212: 0 0 22 0 0 0 0 0 ITS-MSI 134742016 Edge nvme0q0 213: 133098 0 0 0 0 0 0 0 ITS-MSI 134742017 Edge nvme0q1 214: 0 139450 0 0 0 0 0 0 ITS-MSI 134742018 Edge nvme0q2 215: 0 0 139476 0 0 0 0 0 ITS-MSI 134742019 Edge nvme0q3 216: 0 0 0 69767 0 0 0 0 ITS-MSI 134742020 Edge nvme0q4 217: 0 0 0 0 80368 0 0 0 ITS-MSI 134742021 Edge nvme0q5 218: 0 0 0 0 0 77315 0 0 ITS-MSI 134742022 Edge nvme0q6 219: 0 0 0 0 0 0 73022 0 ITS-MSI 134742023 Edge nvme0q7 220: 0 0 0 0 0 0 0 329993 ITS-MSI 134742024 Edge nvme0q8 Signed-off-by:
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Krzysztof Kozlowski authored
Bindings allow a "wake", not "enable", GPIO. Schematics also use WAKE name for the pin: sa8155p-adp.dtb: pcie@1c00000: Unevaluated properties are not allowed ('enable-gpio' was unexpected) Fixes: a1c86c68 ("arm64: dts: qcom: sm8150: Add PCIe nodes") Signed-off-by:
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