- 27 Oct, 2023 3 commits
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Ulf Hansson authored
Merge the mmc fixes for v6.6-rc[n] into the next branch, to allow them to get tested together with the new mmc changes that are targeted for v6.7. Signed-off-by:Ulf Hansson <ulf.hansson@linaro.org>
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Neil Armstrong authored
Document the SDHCI Controller on the SM8650 Platform. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-bindings-sdhci-v2-1-0406fca99033@linaro.orgSigned-off-by:
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Rong Chen authored
For the t7 and older SoC families, the CMD_CFG_ERROR has no effect. Starting from SoC family C3, setting this bit without SG LINK data address will cause the controller to generate an IRQ and stop working. To fix it, don't set the bit CMD_CFG_ERROR anymore. Fixes: 18f92bc0 ("mmc: meson-gx: make sure the descriptor is stopped on errors") Signed-off-by:
Rong Chen <rong.chen@amlogic.com> Reviewed-by:
Jerome Brunet <jbrunet@baylibre.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231026073156.2868310-1-rong.chen@amlogic.comSigned-off-by:
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- 23 Oct, 2023 1 commit
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Aubin Constans authored
On the one hand Eugen has taken responsibilities outside Microchip, on the other hand I have some experience with the Microchip SDMMC SDHCI controller. Change Eugen as reviewer and take over maintainership of the SDHCI MICROCHIP DRIVER. Also, take over maintainership of its predecessor, that is the MCI MICROCHIP DRIVER. Signed-off-by:
Aubin Constans <aubin.constans@microchip.com> Acked-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by:
Eugen Hristev <eugen.hristev@collabora.com> Link: https://lore.kernel.org/r/20230911153246.137148-1-aubin.constans@microchip.comSigned-off-by:
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- 10 Oct, 2023 9 commits
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Rob Herring authored
Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20231006224343.441720-1-robh@kernel.orgSigned-off-by:
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Tomer Maimon authored
Add Nuvoton NPCM BMC sdhci-pltfm controller driver. Signed-off-by:
Tomer Maimon <tmaimon77@gmail.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20231002200610.129799-3-tmaimon77@gmail.comSigned-off-by:
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Tomer Maimon authored
Add binding for Nuvoton NPCM SDHCI controller. Signed-off-by:
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Andy Shevchenko authored
Since we have device_is_compatible() API, drop OF dependency in the driver. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
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Andy Shevchenko authored
The devm_platform_ioremap_resource() and platform_get_irq() print the error messages themselves and our "failed" one brings no value and just noise. Refactor code to avoid those noisy error messages. Signed-off-by:
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Andy Shevchenko authored
The acpi_evaluate_dsm_typed() provides a way to check the type of the object evaluated by _DSM call. Use it instead of open coded variant. Signed-off-by:
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Vincent Whitchurch authored
During board verification, there is a need to test the various supported eMMC/SD speed modes. However, since the framework chooses the best mode supported by the card and the host controller's caps, this currently necessitates changing the devicetree for every iteration. Allow the various speed mode host capabilities to be modified via debugfs in order to allow easier hardware verification. The values to be written are the raw MMC_CAP* values from include/linux/mmc/host.h. This is rather low-level, and these defines are not guaranteed to be stable, but it is perhaps good enough for the intended use case. MMC_CAP_AGGRESSIVE_PM can also be set, in order to be able to re-initialize the card without having to physically remove and re-insert it. /sys/kernel/debug/mmc0# grep timing ios timing spec: 9 (mmc HS200) // Turn on MMC_CAP_AGGRESSIVE_PM and re-trigger runtime suspend /sys/kernel/debug/mmc0# echo $(($(cat caps) | (1 << 7))) > caps /sys/kernel/debug/mmc0# echo on > /sys/bus/mmc/devices/mmc0\:0001/power/control /sys/kernel/debug/mmc0# echo auto > /sys/bus/mmc/devices/mmc0\:0001/power/control // MMC_CAP2_HS200_1_8V_SDR /sys/kernel/debug/mmc0# echo $(($(cat caps2) & ~(1 << 5))) > caps2 /sys/kernel/debug/mmc0# echo on > /sys/bus/mmc/devices/mmc0\:0001/power/control /sys/kernel/debug/mmc0# grep timing ios timing spec: 8 (mmc DDR52) Signed-off-by:
Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20230929-mmc-caps-v2-2-11a4c2d94f15@axis.comSigned-off-by:
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Vincent Whitchurch authored
We want to allow host caps to be changed dynamically via debugfs, so for these to have an effect, ensure that the card type reselection is always applied even if the card is old. Signed-off-by:
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Ben Wolsieffer authored
The STM32 SDMMC peripheral (at least for the STM32F429, STM32F469 and STM32F746, which are all the currently supported devices using periphid 0x00880180) requires DMA to be performed in peripheral flow controller mode. From the STM32F74/5 reference manual, section 35.3.2: "SDMMC host allows only to use the DMA in peripheral flow controller mode. DMA stream used to serve SDMMC must be configured in peripheral flow controller mode" This patch adds a variant option to control peripheral flow control and enables it for the STM32 variant. Signed-off-by:
Ben Wolsieffer <Ben.Wolsieffer@hefring.com> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230928135644.1489691-1-ben.wolsieffer@hefring.comSigned-off-by:
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- 27 Sep, 2023 9 commits
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Ulf Hansson authored
Merge the mmc fixes for v6.6-rc[n] into the next branch, to allow them to get tested together with the new mmc changes that are targeted for v6.7. Signed-off-by: -
Avri Altman authored
The OEMID is an 8-bit binary number rather than 16-bit as the current code parses for. The OEMID occupies bits [111:104] in the CID register, see the eMMC spec JESD84-B51 paragraph 7.2.3. It seems that the 16-bit comes from the legacy MMC specs (v3.31 and before). Let's fix the parsing by simply move to use 8-bit instead of 16-bit. This means we ignore the impact on some of those old MMC cards that may be out there, but on the other hand this shouldn't be a problem as the OEMID seems not be an important feature for these cards. Signed-off-by:
Avri Altman <avri.altman@wdc.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230927071500.1791882-1-avri.altman@wdc.comSigned-off-by:
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Justin Stitt authored
`strncpy` is deprecated for use on NUL-terminated destination strings [1] and as such we should prefer more robust and less ambiguous string interfaces. We expect `vub300->vub_name` to be NUL-terminated based on its uses with format strings: | dev_info(&vub300->udev->dev, "using %s for SDIO offload processing\n", | vub300->vub_name); NUL-padding is not needed. We can see cleaning out vub_name simply consists of: | vub300->vub_name[0] = 0; Considering the above, for all 11 cases a suitable replacement is `strscpy` [2] due to the fact that it guarantees NUL-termination on the destination buffer without unnecessarily NUL-padding. To be clear, there is no existing bug in the current implementation as the string literals are all small enough as to not cause a buffer overread. Nonetheless, this gets us 11 steps closer to removing strncpy uses. Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#strncpy-on-nul-terminated-strings [1] Link: https://manpages.debian.org/testing/linux-manual-4.8/strscpy.9.en.html [2] Link: https://github.com/KSPP/linux/issues/90 Cc: linux-hardening@vger.kernel.org Signed-off-by:
Justin Stitt <justinstitt@google.com> Link: https://lore.kernel.org/r/20230927-strncpy-drivers-mmc-host-vub300-c-v1-1-77426f62eef4@google.comSigned-off-by:
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Ulf Hansson authored
Merge the mmc fixes for v6.6-rc[n] into the next branch, to allow them to get tested together with the new mmc changes that are targeted for v6.7. Signed-off-by: -
Kees Cook authored
Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct jmb38x_ms. [1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci Cc: Maxim Levitsky <maximlevitsky@gmail.com> Cc: Alex Dubov <oakad@yahoo.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Tom Rix <trix@redhat.com> Cc: Len Baker <len.baker@gmx.com> Cc: Dan Carpenter <error27@gmail.com> Cc: "Gustavo A. R. Silva" <gustavoars@kernel.org> Cc: linux-mmc@vger.kernel.org Signed-off-by:
Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20230922175249.work.593-kees@kernel.orgSigned-off-by:
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William Qiu authored
Before, we used syscon to achieve tuning, but the actual measurement showed little effect, so the tuning implementation was modified here, and it was realized by reading and writing the UHS_REG_EXT register. Signed-off-by:
William Qiu <william.qiu@starfivetech.com> Reviewed-by:
Emil Renner Berthing <emil.renner.berthing@canonical.com> Link: https://lore.kernel.org/r/20230922062834.39212-3-william.qiu@starfivetech.comSigned-off-by:
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William Qiu authored
Due to the change of tuning implementation, it's no longer necessary to use the "starfive,sysreg" property in dts, so remove it from required. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Reviewed-by:
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Wenchao Chen authored
By dynamically adjusting the host->hsq_depth, based upon the buffer size being 4k and that we get at least two I/O write requests in flight, we can improve the throughput a bit. This is typical for a random I/O write pattern. More precisely, by dynamically changing the number of requests in flight from 2 to 5, we can on some platforms observe ~4-5% increase in throughput. Signed-off-by:
Wenchao Chen <wenchao.chen@unisoc.com> Link: https://lore.kernel.org/r/20230919074707.25517-3-wenchao.chen@unisoc.com [Ulf: Re-wrote the commitmsg, minor adjustment to the code - all to clarify.] Signed-off-by:
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Wenchao Chen authored
To allow dynamical updates of the current number of used in-flight requests, let's move away from using a hard-coded value to a use a corresponding variable in the struct mmc_host. This can be valuable when optimizing for certain I/O request sequences, as shown by subsequent changes. Signed-off-by:
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- 26 Sep, 2023 13 commits
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Pablo Sun authored
Use atomic readl_poll_timeout_atomic, because msdc_reset_hw may be invoked in IRQ handler in the following context: msdc_irq() -> msdc_cmd_done() -> msdc_reset_hw() The following kernel BUG stack trace can be observed on Genio 1200 EVK after initializing MSDC1 hardware during kernel boot: [ 1.187441] BUG: scheduling while atomic: swapper/0/0/0x00010002 [ 1.189157] Modules linked in: [ 1.204633] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 5.15.42-mtk+modified #1 [ 1.205713] Hardware name: MediaTek Genio 1200 EVK-P1V2-EMMC (DT) [ 1.206484] Call trace: [ 1.206796] dump_backtrace+0x0/0x1ac [ 1.207266] show_stack+0x24/0x30 [ 1.207692] dump_stack_lvl+0x68/0x84 [ 1.208162] dump_stack+0x1c/0x38 [ 1.208587] __schedule_bug+0x68/0x80 [ 1.209056] __schedule+0x6ec/0x7c0 [ 1.209502] schedule+0x7c/0x110 [ 1.209915] schedule_hrtimeout_range_clock+0xc4/0x1f0 [ 1.210569] schedule_hrtimeout_range+0x20/0x30 [ 1.211148] usleep_range_state+0x84/0xc0 [ 1.211661] msdc_reset_hw+0xc8/0x1b0 [ 1.212134] msdc_cmd_done.isra.0+0x4ac/0x5f0 [ 1.212693] msdc_irq+0x104/0x2d4 [ 1.213121] __handle_irq_event_percpu+0x68/0x280 [ 1.213725] handle_irq_event+0x70/0x15c [ 1.214230] handle_fasteoi_irq+0xb0/0x1a4 [ 1.214755] handle_domain_irq+0x6c/0x9c [ 1.215260] gic_handle_irq+0xc4/0x180 [ 1.215741] call_on_irq_stack+0x2c/0x54 [ 1.216245] do_interrupt_handler+0x5c/0x70 [ 1.216782] el1_interrupt+0x30/0x80 [ 1.217242] el1h_64_irq_handler+0x1c/0x2c [ 1.217769] el1h_64_irq+0x78/0x7c [ 1.218206] cpuidle_enter_state+0xc8/0x600 [ 1.218744] cpuidle_enter+0x44/0x5c [ 1.219205] do_idle+0x224/0x2d0 [ 1.219624] cpu_startup_entry+0x30/0x80 [ 1.220129] rest_init+0x108/0x134 [ 1.220568] arch_call_rest_init+0x1c/0x28 [ 1.221094] start_kernel+0x6c0/0x700 [ 1.221564] __primary_switched+0xc0/0xc8 Fixes: ffaea6eb ("mmc: mtk-sd: Use readl_poll_timeout instead of open-coded polling") Signed-off-by:
Pablo Sun <pablo.sun@mediatek.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioachino.delregno@collabora.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230922095348.22182-1-pablo.sun@mediatek.comSigned-off-by:
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Victor Shih authored
When GL9750 enters ASPM L1 sub-states, it will stay at L1.1 and will not enter L1.2. The workaround is to toggle PM state to allow GL9750 to enter ASPM L1.2. Signed-off-by:
Victor Shih <victor.shih@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20230912091710.7797-1-victorshihgli@gmail.comSigned-off-by:
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Claudiu Beznea authored
Document support for the SD Card/MMC interface on the Renesas RZ/G3S (R9A08G045) SoC. Signed-off-by:
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Acked-by:
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Balamanikandan Gunasundar authored
Add description for dma filtering function in struct mci_platform_data. Fixes the warning: Function parameter or member 'dma_filter' not described in 'mci_platform_data'. Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202309020937.C5S2sRnr-lkp@intel.com/Signed-off-by:
Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com> Link: https://lore.kernel.org/r/20230911092540.76334-1-balamanikandan.gunasundar@microchip.comSigned-off-by:
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Julia Lawall authored
for_each_child_of_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. This was done using the Coccinelle semantic patch iterators/for_each_child.cocci Signed-off-by:
Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/20230907095521.14053-6-Julia.Lawall@inria.frSigned-off-by:
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Lad Prabhakar authored
MMC_SDHI_INTERNAL_DMAC config option has dependency on ARM64 and R7S9210/R8A77470 this dependency will keep growing for future SoCs for varying architectures. So to simplify this configuration make MMC_SDHI_INTERNAL_DMAC solely depend on ARCH_RENESAS, as all Renesas SoCs inherently depend on the ARCH_RENESAS config option. This allows selecting MMC_SDHI_INTERNAL_DMAC config option for RZ/Five SoC which is based on RISC-V architecture. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20230901122701.318082-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Haibo Chen authored
Current manual tuning logic only get the first pass window, but this pass window maybe not the best pass window. Now find all the pass window, and chose the largest pass window, and use the average value of this largest pass window to get the best timing. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
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Krzysztof Kozlowski authored
The Qualcomm SDHCI controller lists optional clocks, but still expects fixed order of them and does not allow to skip such clocks if further one in the list is needed. These optional clocks are truly optional, so we need to allow the list to have different orders. The clocks are: - ice: used for Inline Crypto Engine, which is actually separate block and merging it with SDHCI is not a requirement, - bus: clock for SDCC bus frequency voting, - cal and sleep: used for RCLK delay calibration and required for certain platforms for such calibration (as expressed in original commit 4946b3af ("mmc: sdhci-msm: Enable delay circuit calibration clocks")). Only MSM8974pro has these clocks. Relaxing the order fixes dtbs_check warnings: qcom-msm8974pro-fairphone-fp2.dtb: mmc@f9824900: clock-names:3: 'ice' was expected qcom-msm8974pro-fairphone-fp2.dtb: mmc@f9824900: clock-names:4: 'bus' was expected Signed-off-by:
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Ulf Hansson authored
Userspace has currently no way of checking the internal R1 response error bits for some commands. This is a problem for some commands, like RPMB for example. Typically, we may detect that the busy completion has successfully ended, while in fact the card did not complete the requested operation. To fix the problem, let's always poll with CMD13 for these commands and during the polling, let's also aggregate the R1 response bits. Before completing the ioctl request, let's propagate the R1 response bits too. Reviewed-by:
Christian Loehle <christian.loehle@arm.com> Signed-off-by:
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Dan Carpenter authored
Return an error code if sdhci_sprd_get_best_clk_sample() fails. Currently, it returns success. Fixes: d83d251b ("mmc: sdhci-sprd: Add SD HS mode online tuning") Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by:
Baolin Wang <baolin.wang@linux.alibaba.com> Acked-by:
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Sven van Ashbrook authored
To improve the r/w performance of GL9763E, the current driver inhibits LPM negotiation while the device is active. This prevents a large number of SoCs from suspending, notably x86 systems which commonly use S0ix as the suspend mechanism - for example, Intel Alder Lake and Raptor Lake processors. Failure description: 1. Userspace initiates s2idle suspend (e.g. via writing to /sys/power/state) 2. This switches the runtime_pm device state to active, which disables LPM negotiation, then calls the "regular" suspend callback 3. With LPM negotiation disabled, the bus cannot enter low-power state 4. On a large number of SoCs, if the bus not in a low-power state, S0ix cannot be entered, which in turn prevents the SoC from entering suspend. Fix by re-enabling LPM negotiation in the device's suspend callback. Suggested-by:
Stanislaw Kardach <skardach@google.com> Fixes: f9e5b339 ("mmc: host: Improve I/O read/write performance for GL9763E") Cc: stable@vger.kernel.org Signed-off-by:
Sven van Ashbrook <svenva@chromium.org> Acked-by:
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Haibo Chen authored
tuning only support in 4-bit mode or 8 bit mode, so in 1-bit mode, need to hold retuning. Find this issue when use manual tuning method on imx93. When system resume back, SDIO WIFI try to switch back to 4 bit mode, first will trigger retuning, and all tuning command failed. Signed-off-by:
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Krzysztof Kozlowski authored
In the TXT binding before conversion, the "xo" clock was listed as optional. Conversion kept it optional in "clock-names", but not in "clocks". This fixes dbts_check warnings like: qcom-sdx65-mtp.dtb: mmc@8804000: clocks: [[13, 59], [13, 58]] is too short Cc: <stable@vger.kernel.org> Fixes: a4553772 ("dt-bindings: mmc: sdhci-msm: Convert bindings to yaml") Signed-off-by:
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- 24 Sep, 2023 4 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds authored
Pull kvm fixes from Paolo Bonzini: "ARM: - Fix EL2 Stage-1 MMIO mappings where a random address was used - Fix SMCCC function number comparison when the SVE hint is set RISC-V: - Fix KVM_GET_REG_LIST API for ISA_EXT registers - Fix reading ISA_EXT register of a missing extension - Fix ISA_EXT register handling in get-reg-list test - Fix filtering of AIA registers in get-reg-list test x86: - Fixes for TSC_AUX virtualization - Stop zapping page tables asynchronously, since we don't zap them as often as before" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: SVM: Do not use user return MSR support for virtualized TSC_AUX KVM: SVM: Fix TSC_AUX virtualization setup KVM: SVM: INTERCEPT_RDTSCP is never intercepted anyway KVM: x86/mmu: Stop zapping invalidated TDP MMU roots asynchronously KVM: x86/mmu: Do not filter address spaces in for_each_tdp_mmu_root_yield_safe() KVM: x86/mmu: Open code leaf invalidation from mmu_notifier KVM: riscv: selftests: Selectively filter-out AIA registers KVM: riscv: selftests: Fix ISA_EXT register handling in get-reg-list RISC-V: KVM: Fix riscv_vcpu_get_isa_ext_single() for missing extensions RISC-V: KVM: Fix KVM_GET_REG_LIST API for ISA_EXT registers KVM: selftests: Assert that vasprintf() is successful KVM: arm64: nvhe: Ignore SVE hint in SMCCC function ID KVM: arm64: Properly return allocated EL2 VA from hyp_alloc_private_va_range() -
git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-traceLinus Torvalds authored
Pull tracing fixes from Steven Rostedt: - Fix the "bytes" output of the per_cpu stat file The tracefs/per_cpu/cpu*/stats "bytes" was giving bogus values as the accounting was not accurate. It is suppose to show how many used bytes are still in the ring buffer, but even when the ring buffer was empty it would still show there were bytes used. - Fix a bug in eventfs where reading a dynamic event directory (open) and then creating a dynamic event that goes into that diretory screws up the accounting. On close, the newly created event dentry will get a "dput" without ever having a "dget" done for it. The fix is to allocate an array on dir open to save what dentries were actually "dget" on, and what ones to "dput" on close. * tag 'trace-v6.6-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace: eventfs: Remember what dentries were created on dir open ring-buffer: Fix bytes info in per_cpu buffer stats
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git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds authored
Pull cxl fixes from Dan Williams: "A collection of regression fixes, bug fixes, and some small cleanups to the Compute Express Link code. The regressions arrived in the v6.5 dev cycle and missed the v6.6 merge window due to my personal absences this cycle. The most important fixes are for scenarios where the CXL subsystem fails to parse valid region configurations established by platform firmware. This is important because agreement between OS and BIOS on the CXL configuration is fundamental to implementing "OS native" error handling, i.e. address translation and component failure identification. Other important fixes are a driver load error when the BIOS lets the Linux PCI core handle AER events, but not CXL memory errors. The other fixex might have end user impact, but for now are only known to trigger in our test/emulation environment. Summary: - Fix multiple scenarios where platform firmware defined regions fail to be assembled by the CXL core. - Fix a spurious driver-load failure on platforms that enable OS native AER, but not OS native CXL error handling. - Fix a regression detecting "poison" commands when "security" commands are also defined. - Fix a cxl_test regression with the move to centralize CXL port register enumeration in the CXL core. - Miscellaneous small fixes and cleanups" * tag 'cxl-fixes-6.6-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: cxl/acpi: Annotate struct cxl_cxims_data with __counted_by cxl/port: Fix cxl_test register enumeration regression cxl/region: Refactor granularity select in cxl_port_setup_targets() cxl/region: Match auto-discovered region decoders by HPA range cxl/mbox: Fix CEL logic for poison and security commands cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native() PCI/AER: Export pcie_aer_is_native() cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers
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- 23 Sep, 2023 1 commit
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git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linuxLinus Torvalds authored
Pull gpio fixes from Bartosz Golaszewski: - fix an invalid usage of __free(kfree) leading to kfreeing an ERR_PTR() - fix an irq domain leak in gpio-tb10x - MAINTAINERS update * tag 'gpio-fixes-for-v6.6-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: gpio: sim: fix an invalid __free() usage gpio: tb10x: Fix an error handling path in tb10x_gpio_probe() MAINTAINERS: gpio-regmap: make myself a maintainer of it
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