1. 18 May, 2022 3 commits
    • Abhishek Sahu's avatar
      vfio/pci: Virtualize PME related registers bits and initialize to zero · 54918c28
      Abhishek Sahu authored
      If any PME event will be generated by PCI, then it will be mostly
      handled in the host by the root port PME code. For example, in the case
      of PCIe, the PME event will be sent to the root port and then the PME
      interrupt will be generated. This will be handled in
      drivers/pci/pcie/pme.c at the host side. Inside this, the
      pci_check_pme_status() will be called where PME_Status and PME_En bits
      will be cleared. So, the guest OS which is using vfio-pci device will
      not come to know about this PME event.
      
      To handle these PME events inside guests, we need some framework so
      that if any PME events will happen, then it needs to be forwarded to
      virtual machine monitor. We can virtualize PME related registers bits
      and initialize these bits to zero so vfio-pci device user will assume
      that it is not capable of asserting the PME# signal from any power state.
      Signed-off-by: default avatarAbhishek Sahu <abhsahu@nvidia.com>
      Link: https://lore.kernel.org/r/20220518111612.16985-4-abhsahu@nvidia.comSigned-off-by: default avatarAlex Williamson <alex.williamson@redhat.com>
      54918c28
    • Abhishek Sahu's avatar
      vfio/pci: Change the PF power state to D0 before enabling VFs · f4162eb1
      Abhishek Sahu authored
      According to [PCIe v5 9.6.2] for PF Device Power Management States
      
       "The PF's power management state (D-state) has global impact on its
        associated VFs. If a VF does not implement the Power Management
        Capability, then it behaves as if it is in an equivalent
        power state of its associated PF.
      
        If a VF implements the Power Management Capability, the Device behavior
        is undefined if the PF is placed in a lower power state than the VF.
        Software should avoid this situation by placing all VFs in lower power
        state before lowering their associated PF's power state."
      
      From the vfio driver side, user can enable SR-IOV when the PF is in D3hot
      state. If VF does not implement the Power Management Capability, then
      the VF will be actually in D3hot state and then the VF BAR access will
      fail. If VF implements the Power Management Capability, then VF will
      assume that its current power state is D0 when the PF is D3hot and
      in this case, the behavior is undefined.
      
      To support PF power management, we need to create power management
      dependency between PF and its VF's. The runtime power management support
      may help with this where power management dependencies are supported
      through device links. But till we have such support in place, we can
      disallow the PF to go into low power state, if PF has VF enabled.
      There can be a case, where user first enables the VF's and then
      disables the VF's. If there is no user of PF, then the PF can put into
      D3hot state again. But with this patch, the PF will still be in D0
      state after disabling VF's since detecting this case inside
      vfio_pci_core_sriov_configure() requires access to
      struct vfio_device::open_count along with its locks. But the subsequent
      patches related to runtime PM will handle this case since runtime PM
      maintains its own usage count.
      
      Also, vfio_pci_core_sriov_configure() can be called at any time
      (with and without vfio pci device user), so the power state change
      and SR-IOV enablement need to be protected with the required locks.
      Signed-off-by: default avatarAbhishek Sahu <abhsahu@nvidia.com>
      Link: https://lore.kernel.org/r/20220518111612.16985-3-abhsahu@nvidia.comSigned-off-by: default avatarAlex Williamson <alex.williamson@redhat.com>
      f4162eb1
    • Abhishek Sahu's avatar
      vfio/pci: Invalidate mmaps and block the access in D3hot power state · 2b2c651b
      Abhishek Sahu authored
      According to [PCIe v5 5.3.1.4.1] for D3hot state
      
       "Configuration and Message requests are the only TLPs accepted by a
        Function in the D3Hot state. All other received Requests must be
        handled as Unsupported Requests, and all received Completions may
        optionally be handled as Unexpected Completions."
      
      Currently, if the vfio PCI device has been put into D3hot state and if
      user makes non-config related read/write request in D3hot state, these
      requests will be forwarded to the host and this access may cause
      issues on a few systems.
      
      This patch leverages the memory-disable support added in commit
      'abafbc55 ("vfio-pci: Invalidate mmaps and block MMIO access on
      disabled memory")' to generate page fault on mmap access and
      return error for the direct read/write. If the device is D3hot state,
      then the error will be returned for MMIO access. The IO access generally
      does not make the system unresponsive so the IO access can still happen
      in D3hot state. The default value should be returned in this case
      without bringing down the complete system.
      
      Also, the power related structure fields need to be protected so
      we can use the same 'memory_lock' to protect these fields also.
      This protection is mainly needed when user changes the PCI
      power state by writing into PCI_PM_CTRL register.
      vfio_lock_and_set_power_state() wrapper function will take the
      required locks and then it will invoke the vfio_pci_set_power_state().
      Signed-off-by: default avatarAbhishek Sahu <abhsahu@nvidia.com>
      Link: https://lore.kernel.org/r/20220518111612.16985-2-abhsahu@nvidia.comSigned-off-by: default avatarAlex Williamson <alex.williamson@redhat.com>
      2b2c651b
  2. 17 May, 2022 7 commits
  3. 16 May, 2022 1 commit
  4. 13 May, 2022 11 commits
  5. 11 May, 2022 15 commits
  6. 10 May, 2022 1 commit
  7. 08 May, 2022 2 commits
    • Linus Torvalds's avatar
      Linux 5.18-rc6 · c5eb0a61
      Linus Torvalds authored
      c5eb0a61
    • Linus Torvalds's avatar
      Merge tag 'for-5.18/parisc-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux · f002488d
      Linus Torvalds authored
      Pull parisc architecture fixes from Helge Deller:
       "Some reverts of existing patches, which were necessary because of boot
        issues due to wrong CPU clock handling and cache issues which led to
        userspace segfaults with 32bit kernels. Dave has a whole bunch of
        upcoming cache fixes which I then plan to push in the next merge
        window.
      
        Other than that just small updates and fixes, e.g. defconfig updates,
        spelling fixes, a clocksource fix, boot topology fixes and a fix for
        /proc/cpuinfo output to satisfy lscpu"
      
      * tag 'for-5.18/parisc-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
        Revert "parisc: Increase parisc_cache_flush_threshold setting"
        parisc: Mark cr16 clock unstable on all SMP machines
        parisc: Fix typos in comments
        parisc: Change MAX_ADDRESS to become unsigned long long
        parisc: Merge model and model name into one line in /proc/cpuinfo
        parisc: Re-enable GENERIC_CPU_DEVICES for !SMP
        parisc: Update 32- and 64-bit defconfigs
        parisc: Only list existing CPUs in cpu_possible_mask
        Revert "parisc: Fix patch code locking and flushing"
        Revert "parisc: Mark sched_clock unstable only if clocks are not syncronized"
        Revert "parisc: Mark cr16 CPU clocksource unstable on all SMP machines"
      f002488d