- 13 Oct, 2023 11 commits
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Lijo Lazar authored
IP discovery region has increased to > 8K on some SOCs.Maximum reserve size is upto 12K, but not used. For now increase to 10K. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Asad Kamal authored
Use gpu_metrics_v1_4 for SMUv13.0.6 to fill gpu metric info v3: Removed filling gpu metric instantaneous pcie bw Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
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Asad Kamal authored
Add new gpu_metrics_v1_4 to acquire XGMI data transfer, pcie bandwidth & Clock lock status v2: Add pcie error counter to gpu metric table v1_4 Signed-off-by:
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Asad Kamal authored
Update pmfw metric table to include xgmi transfer data and pci instantaneous bandwidth for smu v13_0_6 v2: Updated metric table version v3: Removed inst pcie bw with alignment to metrics table version 8 Signed-off-by:
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Lin.Cao authored
Return -EINVAL when MMSCH init fail which can be handle by function amdgpu_device_reset_sriov correctly. Signed-off-by:
Lin.Cao <lincao12@amd.com> Reviewed-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Signed-off-by:
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Tim Huang authored
Wait for completion of sending the EnableGfxImu message when using the PSP FW loading. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Lang Yu authored
Avoid infinite loop when count is 0. This is missed in rebase. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:274: warning: Function parameter or member 'gart_placement' not described in 'amdgpu_gmc_gart_location' Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Lang Yu authored
MCBP is decided by adev->gfx.mcbp now. This is missed in rebase. Signed-off-by:
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Lang Yu authored
Remove IB end boundary requirement, VPE has no such limitions, use existing amdgpu_ring_generic_pad_ib() instead. This is missed in rebase. Signed-off-by:
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Jay Cornwall authored
When MES is oversubscribed it may not frequently check for new command submissions from driver if the scheduling load is high. Response latency as high as 5 seconds has been observed. Enable a flag which adds a check for new commands between scheduling quantums. Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Cc: Alexandru Tudor <alexandru.tudor@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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- 09 Oct, 2023 29 commits
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Icenowy Zheng authored
SI hardware does not have doorbells at all, however currently the code will try to do the allocation and thus fail, makes SI AMDGPU not usable. Fix this failure by skipping doorbells allocation when doorbells count is zero. Fixes: 54c30d2a ("drm/amdgpu: create kernel doorbell pages") Reviewed-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
Icenowy Zheng <uwu@icenowy.me> Signed-off-by:
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Aaron Liu authored
Enable DCN 3.5.0 support. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Arvind Yadav authored
Here, Adding db_size in byte to find the doorbell's absolute offset for both 32-bit and 64-bit doorbell sizes. So that doorbell offset will be aligned based on the doorbell size. v2: - Addressed the review comment from Felix. v3: - Adding doorbell_size as parameter to get db absolute offset. v4: Squash the two patches into one. Cc: Christian Koenig <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Arvind Yadav <Arvind.Yadav@amd.com> Signed-off-by:
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Christian König authored
bo->tbo.resource can easily be NULL here. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2902Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Aric Cyr authored
This version brings along following fixes: - Refactor DPG test pattern logic for ODM cases - Refactor HWSS into component folder - Revert "drm/amd/display: Add a check for idle power optimization" - Revert "drm/amd/display: remove duplicated edp relink to fastboot - Update cursor limits based on SW cursor fallback limits - Update stream mask - Update pmfw_driver_if new structure - Modify SMU message logs - Don't set dpms_off for seamless boot Known issue: DWB (Writeback functionality) is broken. Fix will be available in DC 3.2.256 Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Stylon Wang authored
[Why] This could work around the issue with DP tunneling producing a NULL pointer dereference. [How] Disable the virtual links. Reviewed-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
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George Shen authored
[Why] Enabling DPG causes HUBP to stay in blank constantly. If DPG is enabled while an MCLK switch is taking place with SubVP, it will cause the MCLK to never complete. This is because SubVP MCLK switch relies a HUBP VLine interrupt, which will never occur when HUBP is constantly in blank. [How] Disable SubVP when test pattern is enabled. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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George Shen authored
[Why] Current DPG test pattern logic does not account for ODM configuration changes after test pattern has already been programmed. For example, if ODM2:1 is enabled after test pattern is already being output, the second pipe is not programmed to output test pattern, causing half the screen to be black. [How] Move DPG test pattern parameter calculations into separate function. Whenever ODM pipe configuration changes, re-calculate DPG test pattern parameters and program DPG if test pattern is currently enabled. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
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Daniel Miess authored
[Why] eDPs fail to light up with seamless boot enabled [How] When seamless boot is enabled don't configure dpms_off in disable_vbios_mode_if_required. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
Daniel Miess <daniel.miess@amd.com> Tested-by:
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Mounika Adhuri authored
[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Mounika Adhuri <moadhuri@amd.com> Tested-by:
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Sung Joon Kim authored
Revert commit 434cf7af ("drm/amd/display: Add a check for idle power optimization") Because it cause Freesync and S4 regression Reviewed-by:
Sung Joon Kim <sungkim@amd.com> Tested-by:
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Yifan Zhang authored
add hub->ctx_distance when read CONTEXT1_CNTL, align w/ write back operation. v2: fix coding style errors reported by checkpatch.pl (Christian) Signed-off-by:
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Nicholas Kazlauskas authored
[Why] These functions can be called from high IRQ levels and the OS will hang if it tries to use a usleep_highres or a msleep. [How] Replace the fsleep with a udelay. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Alvin Lee authored
[Why&How] For determining the cursor size limit, use the same checks that are used for determining SW cursor fallback instead of only using SubVP Reviewed-by:
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Muhammad Ahmed authored
[why] Need to use real clock table [How] Update the clock table Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by:
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Duncan Ma authored
[Why] Whenever stream changes because of new pipe arrangements such as ODM. The new stream mask is not reflected in DMCUB. The mismatch in stream mask is blocking ips entry in some scenarios. [How] Whenever stream arrangement changes, update stream mask and notify DMCUB. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
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Aric Cyr authored
Revert commit 984abb53 ("drm/amd/display: remove duplicated edp relink to fastboot") Because it cause 4k EDP not light up on boot Reviewed-by:
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Max Tseng authored
Fine tune the Vmin clock value Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Max Tseng <max.tseng@amd.com> Tested-by:
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Charlene Liu authored
[why] pmfw header file updated, need align with data structure. [How] Update the data structure. Reviewed-by:
Sung joon Kim <sungjoon.kim@amd.com> Acked-by:
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Muhammad Ansari authored
[WHY] FreeSync spec requires PB8 and PB12 to be set to nominal refresh rate regardless of fixed rate or variable [HOW] Removed the condition that checks and overwrites max refresh rate and set PB8/PB12 to be set to max refresh rate always Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Muhammad Ansari <muhammad.ansari@amd.com> Tested-by:
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Sung Joon Kim authored
[why] It's important to make sure SMU messages are logged by default to improve debugging for power optimization use cases. [how] Change logs to warnings when SMU message returns non-success id. Reviewed-by:
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Stanley.Yang authored
The amdgpu_ras_get_context may return NULL if device not support ras feature, so add check before using. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Yifan Zhang authored
With S/G display becomes stable, enable S/G display for recent APUs by default rather than white list. v2: explicitly disable sg on pre-CZ chips (Alex) v3: add parens for every clause (Alex) Co-authored-by:
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Lijo Lazar authored
Add documentation for the newly added manufacturer and fru_id attributes in sysfs. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lijo Lazar authored
Add support to read Manufacturer Name and FRU File Id fields. Also add sysfs device attributes for external usage. Signed-off-by:
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Lijo Lazar authored
Keep FRU related information together in a separate structure. Signed-off-by:
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Yang Wang authored
v1: enable GFX v9.4.3 FRU device to query board information. v2: use MP1 version to identify different asic Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Boyuan Zhang authored
Update IB starting address alignment and size alignment with correct values for decode and encode IPs. Decode IB starting address alignment: 256 bytes Decode IB size alignment: 64 bytes Encode IB starting address alignment: 256 bytes Encode IB size alignment: 4 bytes Also bump amdgpu driver version for this update. Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
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Gabe Teeger authored
[what] does_configuration_meet_sw_policies check was not done in the validate_only portion of dml2, so some unsupported modes were passing bw validation, only to fail the same check later in validate_and_build. now we add the check to validate_only. Also add line in dcn35_resource to ensure that value set for enable_windowed_mpo_odm gets passed to dml. [why] Immediate black screen during video playback at 4k144hz. The debugger showed that we were failing validation in dml on every updateplanes(). Reviewed-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
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