- 19 Apr, 2017 5 commits
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Olof Johansson authored
Merge tag 'tegra-for-4.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers soc/tegra: Core SoC changes for v4.12-rc1 This contains PMC support for Tegra186 as well as a proper driver for the flow controller found on SoCs up to Tegra210. This also turns the fuse driver into an explicitly non-modular driver. * tag 'tegra-for-4.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: Add initial flowctrl support for Tegra132/210 soc/tegra: flowctrl: Add basic platform driver soc/tegra: Move Tegra flowctrl driver ARM: tegra: Remove unnecessary inclusion of flowctrl header soc: tegra: make fuse-tegra explicitly non-modular soc/tegra: Fix link errors with PMC disabled soc/tegra: Implement Tegra186 PMC support Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'arm-soc-pmdomain' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers ARM SOC PM domain support for 4.12 Dave Gerlach (5): PM / Domains: Add generic data pointer to genpd data struct PM / Domains: Do not check if simple providers have phandle cells dt-bindings: Add TI SCI PM Domains soc: ti: Add ti_sci_pm_domains driver ARM: keystone: Drop PM domain support for k2g * tag 'arm-soc-pmdomain' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: ARM: keystone: Drop PM domain support for k2g soc: ti: Add ti_sci_pm_domains driver dt-bindings: Add TI SCI PM Domains PM / Domains: Do not check if simple providers have phandle cells PM / Domains: Add generic data pointer to genpd data struct Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.pengutronix.de/git/pza/linuxOlof Johansson authored
Reset controller changes for v4.12, part 2 Add reset lines for the NAND and eMMC contollers on LD11/LD20 SoCs. * tag 'reset-for-4.12-2' of git://git.pengutronix.de/git/pza/linux: reset: uniphier: add NAND and eMMC reset control Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'davinci-for-v4.12/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers This adds a new driver for PalmChip PATA controller found on DM6446 and DM6467 SoCs. This should eventually replace the driver in IDE subsystem. The patches have been acked by ATA maintainer. * tag 'davinci-for-v4.12/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: pata_bk3710: clear status bits of BMISP on chipset initialization pata_bk3710: disable IORDY Timer on chipset initialization ata: add Palmchip BK3710 PATA controller driver Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'scpi-update-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/drivers SCPI update for v4.12 Single patch to optimise the completion initialisation using reinit_* API instead of full initialisation on each and every transfer. * tag 'scpi-update-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: firmware: arm_scpi: reinit completion instead of full init_completion() Signed-off-by: Olof Johansson <olof@lixom.net>
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- 04 Apr, 2017 12 commits
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Dave Gerlach authored
K2G will use a different power domain driver than the rest of the keystone family in order to make use of the TI SCI protocol so prevent the standard keystone pm_domain code from registering itself in preparation for a new driver. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Dave Gerlach authored
Introduce a ti_sci_pm_domains driver to act as a generic pm domain provider to allow each device to attach and associate it's ti-sci-id so that it can be controlled through the TI SCI protocol. This driver implements a simple genpd where each device node has a phandle to the power domain node and also must provide an index which represents the ID to be passed with TI SCI representing the device using a single phandle cell. The driver manually parses the phandle to get the cell value. Through this interface the genpd dev_ops start and stop hooks will use TI SCI to turn on and off each device as determined by pm_runtime usage. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Dave Gerlach authored
Add a generic power domain implementation, TI SCI PM Domains, that will hook into the genpd framework and allow the TI SCI protocol to control device power states. Also, provide macros representing each device index as understood by TI SCI to be used in the device node power-domain references. These are identifiers for the K2G devices managed by the PMMC. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Dave Gerlach authored
There is no reason that a platform genpd driver registered using of_genpd_add_provider_simple needs to be constrained to having no cells in the "power-domains" phandle. Currently the genpd framework will fail if any arguments are passed with for a simple provider but the framework does not actually care, so remove the check for phandle argument count. This will allow greater flexibility for genpd providers to use their own arguments that are passed in the phandle and interpret them however they see fit. Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Dave Gerlach authored
Add a void *data pointer to struct generic_pm_domain_data. Because this exists for each device associated with a genpd it will allow us to assign per-device data if needed on a platform for control of that specific device. Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Jon Hunter authored
Tegra132 and Tegra210 support the flowctrl module and so add initial support for these devices. Please note that Tegra186 does not support the flowctrl module, so update the initialisation function such that we do not fall back and attempt to map the 'hardcoded' address range for Tegra186. Furthermore 64-bit Tegra devices have always had the flowctrl node defined in their device-tree and so only use the 'hardcoded' addresses for 32-bit Tegra devices. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Jon Hunter authored
Add a simple platform driver for the flowctrl module so that it gets registered as a proper device. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Jon Hunter authored
The flowctrl driver is required for both ARM and ARM64 Tegra devices and in order to enable support for it for ARM64, move the Tegra flowctrl driver into drivers/soc/tegra. By moving the flowctrl driver, tegra_flowctrl_init() is now called by via an early initcall and to prevent this function from attempting to mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()' is also added. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Jon Hunter authored
The Tegra flowctrl.h header is included unnecessarily by the Tegra sleep.S source file. Remove this unnecessary inclusion. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Paul Gortmaker authored
The Makefiles currently controlling compilation of this code is: drivers/soc/tegra/Makefile:obj-y += fuse/ drivers/soc/tegra/fuse/Makefile:obj-y += fuse-tegra.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modularity so that when reading the driver there is no doubt it is builtin-only. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Arnd Bergmann authored
With the new Tegra186 PMC driver merged, anything that relies on the previous PMC driver fails to link when that is disabled: arch/arm/mach-tegra/pm.o: In function `tegra_pm_set': pm.c:(.text.tegra_pm_set+0x3c): undefined reference to `tegra_pmc_enter_suspend_mode' arch/arm/mach-tegra/pm.o: In function `tegra_suspend_enter': pm.c:(.text.tegra_suspend_enter+0x4): undefined reference to `tegra_pmc_get_suspend_mode' arch/arm/mach-tegra/pm.o: In function `tegra_init_suspend': pm.c:(.init.text+0x1c): undefined reference to `tegra_pmc_get_suspend_mode' pm.c:(.init.text+0x74): undefined reference to `tegra_pmc_set_suspend_mode' ERROR: tegra_powergate_sequence_power_up [drivers/ata/ahci_tegra.ko] undefined! ERROR: tegra_powergate_power_off [drivers/ata/ahci_tegra.ko] undefined! Making the definition depend on the presence of the driver makes it build again, though that might not be the correct fix. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Fixes: 854014236290 ("soc/tegra: Implement Tegra186 PMC support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The power management controller on Tegra186 has changed in backwards- incompatible ways with respect to earlier generations. This implements a new driver that supports inversion of the PMU interrupt as well as the "recovery", "bootloader" and "forced-recovery" reboot commands. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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- 31 Mar, 2017 2 commits
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Alexey Klimov authored
Instead of performing full initialization of the completion structure on each transfer in scpi_send_message(), we initialize it at boot time (more specifically, in the relevant probe() function) and use reinit_completion() to reset ->done counter on each message transfer. Signed-off-by: Alexey Klimov <alexey.klimov@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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http://github.com/Broadcom/stblinuxArnd Bergmann authored
Pull "Broadcom drivers changes for 4.12" from Florian Fainelli: This pull request contains Broadcom ARM-based SoC drivers updates for 4.12, please pull the following changes: - Florian updates the Broadcom STB GISB arbiter driver with a bunch of compatible strings for MIPS-based STBs found under arch/mips/boot/dts/brcm/ in order for the SoC identification driver to recognize these chips * tag 'arm-soc/for-4.12/drivers' of http://github.com/Broadcom/stblinux: soc: bcm: brcmstb: Match additional compatible strings
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- 30 Mar, 2017 4 commits
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Arnd Bergmann authored
Merge tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/drivers Pull "Amlogic driver updates for v4.12" from Kevin Hilman: - firmware: updates/fixes for meson-sm * tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: firmware: meson-sm: Allow 0 as valid return value firmware: meson-sm: Check for buffer output size
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Bartlomiej Zolnierkiewicz authored
Clear IORDYINT, INTRSTAT and DMAERROR bits of BMISP register (value '1' needs to be written to the bit to clear it). Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Bartlomiej Zolnierkiewicz authored
Disable IORDY Timer as the driver doesn't handle IORDY Timer interrupt anyway. Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Bartlomiej Zolnierkiewicz authored
Add Palmchip BK3710 PATA controller driver. Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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- 28 Mar, 2017 1 commit
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Masahiro Yamada authored
Add reset lines for the Denali NAND controller on all UniPhier SoCs, for the Cadence eMMC controller on LD11/LD20 SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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- 23 Mar, 2017 2 commits
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Carlo Caione authored
Some special SMC calls (i.e. the function used to retrieve the serial number of the Amlogic SoCs) returns 0 in the register 0 also when the data was successfully read instead of using the register to hold the number of bytes returned in the bounce buffer as expected. With the current implementation of the driver this is seen as an error and meson_sm_call_read() returns an error even though the data was correctly read. To deal with this when we have no information about the amount of read data (that is 0 is returned by the SMC call) we return to the caller the requested amount of data and 0 as return value. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Carlo Caione authored
After the data is read by the secure monitor driver it is being copied in the output buffer checking only the size of the bounce buffer but not the size of the output buffer. Fix this in the secure monitor driver slightly changing the API. Fix also the efuse driver that it is the only driver using this API to not break bisectability. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # for nvmem Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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- 22 Mar, 2017 2 commits
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Olof Johansson authored
Merge tag 'renesas-drivers-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Renesas ARM Based SoC Drivers Updates for v4.12 * Identify RZ/G1N and RZ/G1H * tag 'renesas-drivers-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: soc: renesas: Identify RZ/G1N soc: renesas: Identify RZ/G1H Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.pengutronix.de/git/pza/linuxOlof Johansson authored
Reset controller changes for v4.12 - make reset drivers with bool Kconfig options explicitly non-modular - fix uniphier non-static symbol warnings - fix socfpga nr_resets property - new drivers for the Arria10 and i.MX7 system reset controllers - fix sunxi 64-bit compilation * tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux: reset: sunxi: fix for 64-bit compilation reset: Add Altera Arria10 SR Reset Controller dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets reset: Add i.MX7 SRC reset driver reset-socfpga: Fix nr_resets property reset: uniphier: fix non static symbol warnings reset: pistachio: make it explicitly non-modular reset: ath79: make it explicitly non-modular reset: oxnas: make it explicitly non-modular reset: meson: make it explicitly non-modular Signed-off-by: Olof Johansson <olof@lixom.net>
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- 15 Mar, 2017 4 commits
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Andre Przywara authored
The Allwinner reset controller has 32-bit registers, so translating the reset cell number into a register and bit offset should not use any architecture dependent data size. Otherwise this breaks for 64-bit architectures like arm64. Fix this by making it clear that it's the hardware register width which matters here in the calculation. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Thor Thayer authored
This patch adds the reset controller functionality for Peripheral PHYs to the Arria10 System Resource Chip. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Thor Thayer authored
The Arria10 System Resource Chip reset controller handles the Arria10 peripheral PHYs. This patch adds the offsets for these PHYs. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Andrey Smirnov authored
Add reset controller driver exposing various reset faculties, implemented by System Reset Controller IP block. Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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- 13 Mar, 2017 2 commits
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Geert Uytterhoeven authored
Add support for identifying the RZ/G1N (r8a7744) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add support for identifying the RZ/G1H (r8a7742) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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- 12 Mar, 2017 5 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/s390/linuxLinus Torvalds authored
Pull s390 fixes from Martin Schwidefsky: - four patches to get the new cputime code in shape for s390 - add the new statx system call - a few bug fixes * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: s390: wire up statx system call KVM: s390: Fix guest migration for huge guests resulting in panic s390/ipl: always use load normal for CCW-type re-IPL s390/timex: micro optimization for tod_to_ns s390/cputime: provide archicture specific cputime_to_nsecs s390/cputime: reset all accounting fields on fork s390/cputime: remove last traces of cputime_t s390: fix in-kernel program checks s390/crypt: fix missing unlock in ctr_paes_crypt on error path
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fixes from Thomas Gleixner: - a fix for the kexec/purgatory regression which was introduced in the merge window via an innocent sparse fix. We could have reverted that commit, but on deeper inspection it turned out that the whole machinery is neither documented nor robust. So a proper cleanup was done instead - the fix for the TLB flush issue which was discovered recently - a simple typo fix for a reboot quirk * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/tlb: Fix tlb flushing when lguest clears PGE kexec, x86/purgatory: Unbreak it and clean it up x86/reboot/quirks: Fix typo in ASUS EeeBook X205TA reboot quirk
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull irq fixes from Thomas Gleixner: - a workaround for a GIC erratum - a missing stub function for CONFIG_IRQDOMAIN=n - fixes for a couple of type inconsistencies * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/crossbar: Fix incorrect type of register size irqchip/gicv3-its: Add workaround for QDF2400 ITS erratum 0065 irqdomain: Add empty irq_domain_check_msi_remap irqchip/crossbar: Fix incorrect type of local variables
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Daniel Borkmann authored
Fengguang reported random corruptions from various locations on x86-32 after commits d2852a22 ("arch: add ARCH_HAS_SET_MEMORY config") and 9d876e79 ("bpf: fix unlocking of jited image when module ronx not set") that uses the former. While x86-32 doesn't have a JIT like x86_64, the bpf_prog_lock_ro() and bpf_prog_unlock_ro() got enabled due to ARCH_HAS_SET_MEMORY, whereas Fengguang's test kernel doesn't have module support built in and therefore never had the DEBUG_SET_MODULE_RONX setting enabled. After investigating the crashes further, it turned out that using set_memory_ro() and set_memory_rw() didn't have the desired effect, for example, setting the pages as read-only on x86-32 would still let probe_kernel_write() succeed without error. This behavior would manifest itself in situations where the vmalloc'ed buffer was accessed prior to set_memory_*() such as in case of bpf_prog_alloc(). In cases where it wasn't, the page attribute changes seemed to have taken effect, leading to the conclusion that a TLB invalidate didn't happen. Moreover, it turned out that this issue reproduced with qemu in "-cpu kvm64" mode, but not for "-cpu host". When the issue occurs, change_page_attr_set_clr() did trigger a TLB flush as expected via __flush_tlb_all() through cpa_flush_range(), though. There are 3 variants for issuing a TLB flush: invpcid_flush_all() (depends on CPU feature bits X86_FEATURE_INVPCID, X86_FEATURE_PGE), cr4 based flush (depends on X86_FEATURE_PGE), and cr3 based flush. For "-cpu host" case in my setup, the flush used invpcid_flush_all() variant, whereas for "-cpu kvm64", the flush was cr4 based. Switching the kvm64 case to cr3 manually worked fine, and further investigating the cr4 one turned out that X86_CR4_PGE bit was not set in cr4 register, meaning the __native_flush_tlb_global_irq_disabled() wrote cr4 twice with the same value instead of clearing X86_CR4_PGE in the first write to trigger the flush. It turned out that X86_CR4_PGE was cleared from cr4 during init from lguest_arch_host_init() via adjust_pge(). The X86_FEATURE_PGE bit is also cleared from there due to concerns of using PGE in guest kernel that can lead to hard to trace bugs (see bff672e6 ("lguest: documentation V: Host") in init()). The CPU feature bits are cleared in dynamic boot_cpu_data, but they never propagated to __flush_tlb_all() as it uses static_cpu_has() instead of boot_cpu_has() for testing which variant of TLB flushing to use, meaning they still used the old setting of the host kernel. Clearing via setup_clear_cpu_cap(X86_FEATURE_PGE) so this would propagate to static_cpu_has() checks is too late at this point as sections have been patched already, so for now, it seems reasonable to switch back to boot_cpu_has(X86_FEATURE_PGE) as it was prior to commit c109bf95 ("x86/cpufeature: Remove cpu_has_pge"). This lets the TLB flush trigger via cr3 as originally intended, properly makes the new page attributes visible and thus fixes the crashes seen by Fengguang. Fixes: c109bf95 ("x86/cpufeature: Remove cpu_has_pge") Reported-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Cc: bp@suse.de Cc: Kees Cook <keescook@chromium.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Alexei Starovoitov <ast@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: lkp@01.org Cc: Laura Abbott <labbott@redhat.com> Cc: stable@vger.kernel.org Link: http://lkml.kernrl.org/r/20170301125426.l4nf65rx4wahohyl@wfg-t540p.sh.intel.com Link: http://lkml.kernel.org/r/25c41ad9eca164be4db9ad84f768965b7eb19d9e.1489191673.git.daniel@iogearbox.netSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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- 11 Mar, 2017 1 commit
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git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds authored
Pull KVM fixes from Radim Krčmář: "ARM updates from Marc Zyngier: - vgic updates: - Honour disabling the ITS - Don't deadlock when deactivating own interrupts via MMIO - Correctly expose the lact of IRQ/FIQ bypass on GICv3 - I/O virtualization: - Make KVM_CAP_NR_MEMSLOTS big enough for large guests with many PCIe devices - General bug fixes: - Gracefully handle exception generated with syndroms that the host doesn't understand - Properly invalidate TLBs on VHE systems x86: - improvements in emulation of VMCLEAR, VMX MSR bitmaps, and VCPU reset * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: nVMX: do not warn when MSR bitmap address is not backed KVM: arm64: Increase number of user memslots to 512 KVM: arm/arm64: Remove KVM_PRIVATE_MEM_SLOTS definition that are unused KVM: arm/arm64: Enable KVM_CAP_NR_MEMSLOTS on arm/arm64 KVM: Add documentation for KVM_CAP_NR_MEMSLOTS KVM: arm/arm64: VGIC: Fix command handling while ITS being disabled arm64: KVM: Survive unknown traps from guests arm: KVM: Survive unknown traps from guests KVM: arm/arm64: Let vcpu thread modify its own active state KVM: nVMX: reset nested_run_pending if the vCPU is going to be reset kvm: nVMX: VMCLEAR should not cause the vCPU to shut down KVM: arm/arm64: vgic-v3: Don't pretend to support IRQ/FIQ bypass arm64: KVM: VHE: Clear HCR_TGE when invalidating guest TLBs
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