- 01 Dec, 2023 3 commits
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Mika Kahola authored
With TBT-ALT mode we are not programming C20 chip PLL's and hence we don't need to check state verification. We don't need to program DP link signal levels i.e.pre-emphasis and voltage swing either. This patch fixes dmesg errors like this one "[drm] ERROR PHY F Write 0c06 failed after 3 retries." Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Reviewed-by:
Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231129122221.1109084-1-mika.kahola@intel.com
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Jani Nikula authored
Avoid bool/int mismatches in state checker macros. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231129173317.1192269-2-jani.nikula@intel.com
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Jani Nikula authored
Don't treat bools as integers. v2: Rebase Signed-off-by:
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- 29 Nov, 2023 10 commits
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Clint Taylor authored
DDC pin mapping for DGFX cards uses direct VBT pin mapping Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Clint Taylor <clinton.a.taylor@intel.com> Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128190329.1335562-1-lucas.demarchi@intel.comSigned-off-by:
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Balasubramani Vivekanandan authored
WAs 14011508470, 14011503030 were applied on IP versions beyond which they are applicable. Fixed the IP version checks for these workarounds. Signed-off-by:
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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heminhong authored
Current, the dewake_scanline variable is defined as unsigned int, an unsigned int variable that is always greater than or equal to 0. when _intel_dsb_commit function is called by intel_dsb_commit function, the dewake_scanline variable may have an int value. So the dewake_scanline variable is necessary to defined as an int. Fixes: f83b94d2 ("drm/i915/dsb: Use DEwake to combat PkgC latency") Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202310052201.AnVbpgPr-lkp@intel.com/ Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by:
heminhong <heminhong@kylinos.cn> Reviewed-by:
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Rahul Rameshbabu authored
Dump the iir value in hex when the interrupt is unexpected. Link: https://gitlab.freedesktop.org/drm/intel/-/issues/9652#note_2178501 Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Rahul Rameshbabu <sergeantsagara@protonmail.com> Reviewed-by:
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by:
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Ville Syrjälä authored
Use the >= and < operators for the DISPLAY_VER checks everywhere. This is what most of the code does, but especially recently random pieces of code have started doing this differently for no good reason. Conversion done with the following cocci: @find@ expression i915; constant ver; @@ ( DISPLAY_VER(i915) <= ver | DISPLAY_VER(i915) > ver ) @script:python inc@ old_ver << find.ver; new_ver; @@ coccinelle.new_ver = str(int(old_ver) + 1) @@ expression find.i915; constant find.ver; identifier inc.new_ver; @@ ( - DISPLAY_VER(i915) <= ver + DISPLAY_VER(i915) < new_ver | - DISPLAY_VER(i915) > ver + DISPLAY_VER(i915) >= new_ver ) Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231127145028.4899-4-ville.syrjala@linux.intel.comReviewed-by:
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Ville Syrjälä authored
We have no bigjoiner support in the MST code, so .mode_valid() pretending otherwise is just going to result black screens for users. Reject any mode that needs the joiner. Cc: stable@vger.kernel.org Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: d51f25eb ("drm/i915: Add DSC support to MST path") Signed-off-by:
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Ville Syrjälä authored
.mode_valid_ctx() returns an errno, not the mode status. Fix the code to do the right thing. Cc: stable@vger.kernel.org Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: d51f25eb ("drm/i915: Add DSC support to MST path") Signed-off-by:
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Ville Syrjälä authored
Apparently some BXT/GLK systems have DSI panels whose timings don't agree with the normal cpu transcoder hblank>=32 limitation. This is perhaps fine as there are no specific hblank/etc. limits listed for the BXT/GLK DSI transcoders. Move those checks out from the global intel_mode_valid() into into connector specific .mode_valid() hooks, skipping BXT/GLK DSI connectors. We'll leave the basic [hv]display/[hv]total checks in intel_mode_valid() as those seem like sensible upper limits regardless of the transcoder used. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9720 Fixes: 8f4b1068 ("drm/i915: Check some transcoder timing minimum limits") Signed-off-by:
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Ville Syrjälä authored
Currently no one can figure out what the PSR code is doing since we're including any of it in the basic state dump. Add at least the bare minimum there. v2: Also dump has_panel_replay (Jouni) Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
Jouni Högander <jouni.hogander@intel.com>
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Vinod Govindapillai authored
In earlier versions, FBC was restricted if PSR2 is enabled. From xe2lpd onwards no such restrictions are needed anymore. HSD: 14014305387 Signed-off-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by:
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- 27 Nov, 2023 2 commits
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Jouni Högander authored
Currently we are enabling selective fetch for all planes that are visible. This is suboptimal as we might be fetching for memory for planes that are not part of selective update. Fix this by adding proper handling for disabling plane selective fetch: If plane previously part of selective update is now not part of update: Add it into updated planes and let the plane configuration to disable selective fetch for it. v3: Checkpatch warnings fixed v2: - Add setting sel_fetch_area->y1/y2 to -1 - Remove setting again local sel_fetch_area variable Signed-off-by:
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Jouni Högander authored
Currently selective fetch configuration for planes is implemented in psr code. More suitable place for this code is where everything else is configured for planes -> move it into skl_universal_plane.c and intel_cursor.c. This also allows us to drop hooks for cursor handling. v3: Checkpatch warnings fixed v2: Removed setting sel_fetch_area->y1/y2 as -1 Signed-off-by:
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- 24 Nov, 2023 2 commits
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Ville Syrjälä authored
Adding ad-hoc debug prints all over the place is not good. Move the SDP split debug spew into the proper place (state dumper). Signed-off-by:
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Ville Syrjälä authored
Print the pipe name in ascii rather than hex. Signed-off-by:
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- 23 Nov, 2023 20 commits
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Ville Syrjälä authored
The current implementation of change_lut_val_precision() is just a convoluted way of shifting by 8. Implement the proper rounding by just using drm_color_lut_extract() and intel_color_lut_pack() like everyone else does. And as the uapi can't handle >=1.0 values but the hardware can we need to clamp the results appropriately in the readout path. Signed-off-by:
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Ville Syrjälä authored
Use min() instead of clamp() since the color values involved are unsigned. No functional changes. Signed-off-by:
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Ville Syrjälä authored
drm_color_lut_extract() rounding was changed to follow the OpenGL int<->float conversion rules. Adjust intel_color_lut_pack() to match. Signed-off-by:
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Ville Syrjälä authored
The current implementation of drm_color_lut_extract() generates weird results. Eg. if we go through all the values for 16->8bpc conversion we see the following pattern: in out (count) 0 - 7f -> 0 (128) 80 - 17f -> 1 (256) 180 - 27f -> 2 (256) 280 - 37f -> 3 (256) ... fb80 - fc7f -> fc (256) fc80 - fd7f -> fd (256) fd80 - fe7f -> fe (256) fe80 - ffff -> ff (384) So less values map to 0 and more values map 0xff, which doesn't seem particularly great. To get just the same number of input values to map to the same output values we'd just need to drop the rounding entrirely. But perhaps a better idea would be to follow the OpenGL int<->float conversion rules, in which case we get the following results: in out (count) 0 - 80 -> 0 (129) 81 - 181 -> 1 (257) 182 - 282 -> 2 (257) 283 - 383 -> 3 (257) ... fc7c - fd7c -> fc (257) fd7d - fe7d -> fd (257) fe7e - ff7e -> fe (257) ff7f - ffff -> ff (129) Note that since the divisor is constant the compiler is able to optimize away the integer division in most cases. The only exception is the _ULL() case on 32bit architectures since that gets emitted as inline asm via do_div() and thus the compiler doesn't get to optimize it. Signed-off-by:
Maxime Ripard <mripard@kernel.org>
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Juha-Pekka Heikkila authored
We are preparing for Xe driver. I915 and Xe object implementation are differing. Use intel_bo_to_drm_bo instead of &obj->base. Signed-off-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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Juha-Pekka Heikkila authored
touch dpt_vma->node only if dpt-vma is not NULL Signed-off-by:
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Juha-Pekka Heikkila authored
Here created intel_dpt_common.c to hold intel_dpt_configure which is needed for both xe and i915. Signed-off-by:
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Ville Syrjälä authored
There's no real reason why we'd need a full modeset for audio changes. So let's allow audio to be toggled during fastset. In case the ELD changes while has_audio isn't changing state we force both audio disable and enable so the new ELD gets propagated to the audio driver. Reviewed-by:
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Ville Syrjälä authored
Relocate the audio enable/disable from the full modeset hooks into the common pre/post plane update stage of the commit. Audio fastset is within easy reach now. Reviewed-by:
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Ville Syrjälä authored
Push the encoder->audio_{enable,disable}() calls out from the encoder->{enable,disable}() hooks. Moving towards audio fastset. Reviewed-by: -
Ville Syrjälä authored
Add encoder vfuncs for audio enable/disable. This will allow audio to be enabled/disabled during fastsets. An encoder hook is necessary as on pre-hsw platforms different encoder types implement audio in different ways. Reviewed-by:
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Ville Syrjälä authored
Follow the hsw+ approach toggle the audio presence detect when we set up the ELD, instead of doing it when turning the port on/off. This will facilitate audio enable/disable to happen during fastsets instead of requiring a full modeset. Reviewed-by:
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Ville Syrjälä authored
Follow the hsw+ approach toggle the audio presence detect when we set up the ELD, instead of doing it when turning the port on/off. This will facilitate audio enable/disable to happen during fastsets instead of requiring a full modeset. Reviewed-by:
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Ville Syrjälä authored
Put a wrapper around the intel_audio_codec_{enable,disable}() calls in the g4x+ DP/HDMI code. We shall move the presence detect enable/disable into the wrappers later. Reviewed-by: -
Ville Syrjälä authored
Push the audio enable/disable to be the last/first thing respectively that is done in the encoder enable/disable hooks. The goal is to move it further out of these encoder hooks entirely. Reviewed-by:
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Ville Syrjälä authored
Doing the if-else around RMWs is kinda silly. Just set/clear the apporiate bits with a single RMW. Also unify the coding style a bit icl_wa_cursorclkgating() while at it. Reviewed-by:
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Ville Syrjälä authored
We used to call intel_pre_plane_updates() for any pipe going through a modeset whether the pipe was previously enabled or not. This in fact needed to apply all the necessary clock gating workarounds/etc. Restore the correct behaviour. Fixes: 39919997 ("drm/i915: Disable all planes before modesetting any pipes") Reviewed-by:
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Ville Syrjälä authored
{planes,vrr}_{enabling,disabling}() are supposed to indicate whether the specific hardware feature is supposed to be enabling or disabling. That can only makes sense if the pipe is active overall. So check for that before we go poking at the hardware. I think we're semi-safe currently on due to: - intel_pre_plane_update() doesn't get called when the pipe was not-active prior to the commit, but this is actually a bug. This saves vrr_disabling(), and vrr_enabling() is called from deeper down where we have already checked hw.active. - active_planes mirrors the crtc's hw.active Reviewed-by: -
Jouni Högander authored
Do not continue to psr2 checks if psr or panel replay is not supported. Cc: Animesh Manna <animesh.manna@intel.com> Fixes: b8cf5b5d ("drm/i915/panelreplay: Initializaton and compute config for panel replay") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9670Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231120130214.3332726-1-jouni.hogander@intel.com
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Mika Kahola authored
entry_setup_frames variable is defined as u8. However, the function call intel_psr_entry_setup_frames() can return negative error code. There is a type mismatch here, so let's switch to use int here as well. Fixes: 2b981d57 ("drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier") Signed-off-by:
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- 22 Nov, 2023 3 commits
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Andy Shevchenko authored
Drop unused vlv_iosf_sb_read() and vlv_iosf_sb_write(). Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Hans de Goede <hdegoede@redhat.com> Reviewed-by:
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Andy Shevchenko authored
For a couple of cases the branches call the same bxt_gpio_set_value(). As Ville suggested they can be combined by dropping the DISPLAY_VER() check from Gen 11 to Gen 9. Do it that way. Suggested-by:
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Andy Shevchenko authored
It's a dirty hack in the driver that pokes GPIO registers behind the driver's back. Moreoever it might be problematic as simultaneous I/O may hang the system, see the commit 0bd50d71 ("pinctrl: cherryview: prevent concurrent access to GPIO controllers") for the details. Taking all this into consideration replace the hack with proper GPIO APIs being used. Signed-off-by:
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