- 04 May, 2022 16 commits
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Likun Gao authored
Unify hdp related function into hdp structure for hdp version 6. V2: Remove hdp invalidate function as hdp v6 doesn't have read cache. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Philip Yang authored
To cleanup the BOs of bo_list which have got user pages. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Hawking Zhang authored
Add hdp v6_0_0 register offset and shift masks header files (Hawking) Signed-off-by:
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pengfuyuan authored
Fix spelling typo in comments. Signed-off-by:
pengfuyuan <pengfuyuan@kylinos.cn> Signed-off-by:
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Minghao Chi authored
Simplify the return expression. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Minghao Chi <chi.minghao@zte.com.cn> Signed-off-by:
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Minghao Chi authored
Simplify the return expression. Reported-by:
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Likun Gao authored
Enable IH v6 on asics where it is present. Signed-off-by:
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Stanley.Yang authored
This adds ih v6_0 ip block support. IH is the interrupt handler. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Likun Gao authored
Only V13.0.2 on SMU v13 will get 0 based max level from fw and increment by one, other ASIC will not need for this. V2: replace the asic_type check with ip versioning check. Signed-off-by:
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Stanley Yang authored
Define soc21 ih clientid Signed-off-by:
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Hawking Zhang authored
Add osssys v6_0_0 register offset and shift masks header files (Hawking) Signed-off-by:
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Likun Gao authored
Enable NBIO 4.3 on asics where it is present. Signed-off-by:
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Stanley.Yang authored
This adds nbio v4_3_0 ip block support Changed from v1: use WREG32_SOC15/RREG32_SOC15 instead of WREG32_PCIE/RREG32_PCIE remove the programming of PCIE_CONFIG_CNTL Signed-off-by:
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Hawking Zhang authored
Add nbio v4_3_0 register offset and shift masks header files (Hawking) Signed-off-by:
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Likun Gao authored
Enable soc21 common support on asics where it is present. Signed-off-by:
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Harry Wentland authored
A faulty receiver might report an erroneous channel count. We should guard against reading beyond AUDIO_CHANNELS_COUNT as that would overflow the dpcd_pattern_period array. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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- 28 Apr, 2022 24 commits
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Philip Yang authored
Otherwise userspace resubmit the BOs again will trigger kernel WARNING and fail the command submission. Signed-off-by:
Robert Święcki <robert@swiecki.net> Reviewed-by:
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Candice Li authored
Remove the redundant codes to fix build warning when CONFIG_DEBUG_FS is disabled. Reported-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Stanley.Yang authored
This adds soc21 common ip block support Changed from v1: Switch WREG32/RREG32_PCIE to use indirect reg access helper for sco15 and onwards Acked-by:
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Stanley.Yang authored
add new write field macro to handle soc21 registers with reg prefix Acked-by:
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Hawking Zhang authored
Add nbio callback func used to query rom offset. Used to query the rom offset for fetching the vbios. Acked-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Hawking Zhang authored
Add gc v11_0_0 register offset and shift masks header files (Hawking) Acked-by:
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Hawking Zhang authored
Add mp v13_0_0 register offset and shift masks header files (Hawking) Acked-by:
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Hawking Zhang authored
Handle atom_gfx_info_v3_0 structure. Signed-off-by:
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Hawking Zhang authored
Handle newer gc info tables. Signed-off-by:
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Hawking Zhang authored
atomfirmware table used for newer gfx IPs. Signed-off-by:
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Hawking Zhang authored
vram_info table provides various vram information including vram_vendor, vram_type, vram_width, etc. v2: correct the calculation of vram_width Signed-off-by:
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Hawking Zhang authored
To support query vram_width, vram_type, vram_vendor information Signed-off-by:
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Hawking Zhang authored
Some initial settings now are not available from the atom data table. The assumption that !ps[0] || !ps[1] in amdgpu_atom_asic_init is not valid. In addition, driver needs to strictly follow atomfirmware structure (asic_init_parameters) to initialize parameters used to execute asic_init function, otherwise, the execution of asic_init would fail. This shall be applicable to all soc15 adapters,but let make the transition on soc21 first. Signed-off-by:
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Hawking Zhang authored
Add helper function to execute atomfirmware asic_init from the cmd table Signed-off-by:
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Alex Deucher authored
This data has no dependencies, so encapsulate it all within amdgpu_discovery.c. Acked-by:
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Alex Deucher authored
To get the codec disable fuse mask. Acked-by:
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Alex Deucher authored
Check the table signatures and checksums and verify that the tables exist before accessing them. v2: disable MALL table for now Acked-by:
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Alex Deucher authored
Add a function to fetch the mall size from the IP discovery table. Properly handle harvest configurations where more or less cache may be available. Acked-by:
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Alex Deucher authored
Check the harvesting table to determing if any UMC blocks have been harvested. Acked-by:
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Alex Deucher authored
For chips with IP discovery get this from the table, hardcode it for older asics. Acked-by:
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Alex Deucher authored
This will be useful in future patches. Acked-by:
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Alex Deucher authored
The table is in little endian format. Acked-by:
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Guchun Chen authored
Disable runtime power management on several sienna cichlid cards, otherwise SMU will possibly fail to be resumed from runtime suspend. Will drop this after a clean solution between kernel driver and SMU FW is available. amdgpu 0000:63:00.0: amdgpu: GECC is enabled amdgpu 0000:63:00.0: amdgpu: SECUREDISPLAY: securedisplay ta ucode is not available amdgpu 0000:63:00.0: amdgpu: SMU is resuming... amdgpu 0000:63:00.0: amdgpu: SMU: I'm not done with your command: SMN_C2PMSG_66:0x0000000E SMN_C2PMSG_82:0x00000080 amdgpu 0000:63:00.0: amdgpu: Failed to SetDriverDramAddr! amdgpu 0000:63:00.0: amdgpu: Failed to setup smc hw! [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <smu> failed -62 amdgpu 0000:63:00.0: amdgpu: amdgpu_device_ip_resume failed (-62) v2: seperate to a function. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
From the GC info table to the gfx config structure in the driver. The driver will use this data to configure the card correctly. Acked-by:
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