- 22 Apr, 2017 9 commits
-
-
Markus Elfring authored
The script "checkpatch.pl" pointed information out like the following. * CHECK: Comparison to NULL could be written "!drvdata" Thus adjust this expression. * WARNING: Possible unnecessary 'out of memory' message Thus remove such a statement here. Signed-off-by:
Markus Elfring <elfring@users.sourceforge.net> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
-
Markus Elfring authored
Multiplications for the size determination of memory allocations indicated that array data structures should be processed. Thus use the corresponding function "devm_kcalloc". This issue was detected by using the Coccinelle software. Signed-off-by:
-
Markus Elfring authored
Multiplications for the size determination of memory allocations indicated that array data structures should be processed. Thus use the corresponding function "kcalloc". This issue was detected by using the Coccinelle software. Signed-off-by:
-
John Crispin authored
Add the missing reset bits of the ethsys core to the mt2701-reset include file, so that we can reference them from within a devicetree file. Signed-off-by:
John Crispin <john@phrozen.org> Signed-off-by:
-
John Crispin authored
The ethernet clock core has a reset register that is currently not exposed to the user. Fix this by adding the missing registration code. Signed-off-by:
-
Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into HEAD Pull Allwinner clock changes, take 2 from Maxime Ripard: A few minor bug and comment fixes, plus some fixes for the PRCM CCU driver merged in the prior pull request * tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch clk: sunxi-ng: use 1 as fallback for minimum multiplier clk: sunxi-ng: fix PRCM CCU CLK_NUMBER value clk: sunxi-ng: fix PRCM CCU ir clk parent
-
Daniel Lezcano authored
The hi655x multi function device is a PMIC providing regulators. The PMIC also provides a clock for the WiFi and the Bluetooth, let's implement this clock in order to add it in the hi655x MFD and allow proper wireless initialization. Signed-off-by:
Daniel Lezcano <daniel.lezcano@linaro.org> [sboyd@codeaurora.org: Remove clkdev usage] Signed-off-by:
-
Arnd Bergmann authored
When CONFIG_ATAGS or CONFIG_OMAP3 is disabled, we get a build error: In file included from include/linux/clk-provider.h:15:0, from drivers/clk/ti/clk.c:19: drivers/clk/ti/clk.c: In function 'ti_clk_add_aliases': drivers/clk/ti/clk.c:438:29: error: 'simple_clk_match_table' undeclared (first use in this function); did you mean 'simple_attr_write'? Moving the match table down fixes it. Fixes: c17435c5 ("clk: ti: add API for creating aliases automatically for simple clock types") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Acked-by:
Tero Kristo <t-kristo@ti.com> Signed-off-by:
-
Arnd Bergmann authored
When none of the OMAP4-generation SoCs are enabled, we run into a link error for am43xx/am43xx: drivers/clk/ti/dpll.o: In function `of_ti_am3_dpll_x2_setup': dpll.c:(.init.text+0xd8): undefined reference to `clkhwops_omap4_dpllmx' This is easily fixed by adding another #ifdef. While looking at the code, I also spotted another problem with the assignment of hw_ops variable that is not used again later. I'm changing this to setting clk_hw->ops instead, which I guess is what was intended here. Fixes: 473adbf4 ("clk: ti: dpll44xx: fix clksel register initialization") Signed-off-by:
-
- 19 Apr, 2017 25 commits
-
-
Markus Elfring authored
The script "checkpatch.pl" pointed information out like the following. CHECK: 'seperated' may be misspelled - perhaps 'separated'? Thus rename the affected variable. Signed-off-by:
-
Markus Elfring authored
The script "checkpatch.pl" pointed information out like the following. WARNING: Possible unnecessary 'out of memory' message Thus remove such statements here. Signed-off-by:
-
Markus Elfring authored
* A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "kcalloc". This issue was detected by using the Coccinelle software. * Replace the specification of a data type by a pointer dereference to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by:
-
Markus Elfring authored
The script "checkpatch.pl" pointed information out like the following. WARNING: Possible unnecessary 'out of memory' message Thus remove such statements here. Signed-off-by:
-
Markus Elfring authored
* A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "devm_kmalloc_array". This issue was detected by using the Coccinelle software. * Replace the specification of a data type by a pointer dereference to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by:
-
Markus Elfring authored
* A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "kcalloc". This issue was detected by using the Coccinelle software. * Replace the specification of a data type by a pointer dereference to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by:
-
Kuninori Morimoto authored
cs2000 can select Static/Dynamic ratio based Frequency Synthesizer Mode, it can select 20.12 High Multiplier interpret for 32-bit User Defined Ratio if Dynamic ratio mode. Otherwise it should select 12.20 High Accuracy mode. Current cs2000 is supporting Static ratio mode only, so it should select 12.20 High Accuracy mode, not 20.12 High Multiplier mode. This patch fixes it. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
-
Kuninori Morimoto authored
DEVICE_CFG2 can select ratio from user defined ratio and LOCKCLK is for it. But current driver sets fixed 0 value. This patch fixes it. Note is that current cs2000 driver is using/supporting only ratio0 (= ch0) now. DEVICE_CFG2 can select STATIC/DYNAMIC ratio mode, and current cs2000 driver is selecting STATIC mode, but it was not understandable on current code. This patch also solve this issue. Signed-off-by:
-
Kuninori Morimoto authored
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses for up to 20 ms (t CS) at a time. This patch enables it Signed-off-by:
-
Stanimir Varbanov authored
Make venus_gdsc parent of venus gdsc core0 and core1. Signed-off-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by:
-
Pierre-Louis Bossart authored
Due to timing requirements, TI and Conexant manage the audio reference clock from their ASoC codec drivers using the "mclk" string. This patch adds another lookup for the "pmc_plt_clk_3" clock to avoid Intel-specific tests in those codec drivers and use code as-is. To avoid a leak, clk_add_alias() is not used in this patch. Instead the lookup is created manually as part of the .probe() step and dropped in the .remove() step. "pmc_plt_clk_3" is used exclusively for audio on all known Baytrail/CherryTrail designs and is e.g. routed on the MCLK (pin 26) of the MinnowBoardMAX Turbot LSE connector. Signed-off-by:
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by:
-
Bharat Kumar Reddy Gooty authored
Corrected the bits for power and iso. Signed-off-by:
Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by:
Jon Mason <jon.mason@broadcom.com> Fixes: f7225a83 ("clk: ns2: add clock support for Broadcom Northstar 2 SoC") Signed-off-by:
-
Srinivas Kandagatla authored
rpm branch clk rate should requested as either 0 or 1 but not INT_MAX. This patch fixes rate request for branch clocks during clk handoff. Suggested-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
-
Stefan Agner authored
The USDHC NAND root clock is not gated by any CCM clock gate. Remove the bogus gate definition. Signed-off-by:
Stefan Agner <stefan@agner.ch> Acked-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
-
Thomas Petazzoni authored
There is no SPEAr600 device named "adc". Instead, the description of the ADC was recently added to the Device Tree, and the device name is "d820b000.adc", so we should associate the ADC gatable clock to this device name. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
-
Kevin-CW Chen authored
Add MT6797 clock support, include topckgen, apmixedsys, infracfg and subsystem clocks Signed-off-by:
Kevin-CW Chen <kevin-cw.chen@mediatek.com> Signed-off-by:
Mars Cheng <mars.cheng@mediatek.com> Tested-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
-
Kevin-CW Chen authored
This patch adds the binding documentation for apmixedsys, imgsys, infracfg, mmsys, topckgen, vdecsys and vencsys for MT6797. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
Stephen Boyd authored
* clk-mt6797: clk: mediatek: add mt6797 clock IDs
-
Mars Cheng authored
Signed-off-by:
-
Dong Aisheng authored
Add the missing ipg_root_clk which actually is already used by many orphan clks in current tree. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
-
Dong Aisheng authored
MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200 used actually is for adc, not ahb. After fix, correct ocram_s_clk parent accordingly as well. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
-
Alexey Firago authored
Update IDT VersaClock 5 driver to support 5P49V5935. This chip has two clock inputs (internal XTAL or external CLKIN), four fractional dividers (FODs) and five clock outputs (four universal clock outputs and one reference clock output at OUT0_SELB_I2C). Current driver supports up to 2 FODs and up to 3 clock outputs. This patch sets max number of supported FODs to 4 and max number of supported clock outputs to 5. Signed-off-by:
Alexey Firago <alexey_firago@mentor.com> Reviewed-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
-
Alexey Firago authored
IDT VersaClock 5 5P49V5935 has 4 clock outputs, 4 fractional dividers. Input clock source can be taken from either integrated crystal or from external reference clock. Signed-off-by:
-
Alexey Firago authored
Introduce vc5_chip_info structure to describe features of a particular VC5 chip (id, number of FODs, number of outputs, flags). For now flags are only used to indicate if chip has internal XTAL. vc5_chip_info is set on probe from the matched of_device_id->data. Also add defines to specify maximum number of FODs and clock outputs supported by the driver. With these changes it should be easier to extend driver to support more VC5 models. Signed-off-by:
-
Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull Allwinner clock patches for 4.12 from Maxime Ripard: Support for the new H5 SoC and the PRCM block found in a number of SoCs as well, plus the usual chunk of fixes and minor enhancements. * tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Display index when clock registration fails clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks clk: sunxi-ng: mult: Support PLL lock detection clk: sunxi-ng: add support for PRCM CCUs dt-bindings: update device tree binding for Allwinner PRCM CCUs clk: sunxi-ng: sun5i: Fix mux width for csi clock clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver clk: sunxi-ng: gate: Support common pre-dividers
-
- 17 Apr, 2017 2 commits
-
-
Stephen Boyd authored
* clk-fixes: clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
-
Stephen Boyd authored
Merge tag 'sunxi-clk-fixes-for-4.11-2-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull Allwinner clock fixes for 4.11 from Maxime Ripard: Two build errors fixes for the sunxi-ng drivers. The two other patches fix random CPU crashes happening on the A33 since CPUFreq has been enabled in 4.11. * tag 'sunxi-clk-fixes-for-4.11-2-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER
-
- 13 Apr, 2017 4 commits
-
-
Chen-Yu Tsai authored
We ignore the d1 and d2 dividers in the audio PLL, and force them to 1 (register value 0) at probe time. However the comment preceding the audio PLL definition says we enforce the default value, which is not the same. Fix the preceding comment to match what we do in code. Fixes: b8eb71dc ("clk: sunxi-ng: Add A80 CCU") Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
-
Chen-Yu Tsai authored
In commit 2beaa601 ("clk: sunxi-ng: Implement minimum for multipliers"), the multiplier minimums in the set_rate callback for NM and NKMP style clocks were not updated. This patch fixes them to match their round_rate callbacks. Fixes: 2beaa601 ("clk: sunxi-ng: Implement minimum for multipliers") Signed-off-by:
-
Chen-Yu Tsai authored
A zero multiplier does not make sense for clocks. Use 1 as the minimum when a multiplier minimum isn't specified. Fixes: 2beaa601 ("clk: sunxi-ng: Implement minimum for multipliers") Signed-off-by:
-
Chen-Yu Tsai authored
This patch utilizes the new PLL clk notifier to gate then ungate the PLL CPU clock after rate changes. This should mitigate the system hangs observed after the introduction of cpufreq for the A33. Signed-off-by:
Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by:
-
