- 03 Oct, 2019 40 commits
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Jiange Zhao authored
Add Navi12 PCI id support. v2: flag as experimental for now (Alex) Signed-off-by:
Jiange Zhao <Jiange.Zhao@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Tianci.Yin authored
update registers: mmUTCL1_CTRL Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
update registers: mmUTCL1_CTRL Reviewed-by:
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Alex Deucher authored
We can remove this later as things get closer to launch. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Alex Deucher authored
Otherwise we may get stale data. Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Alex Deucher authored
We need to make sure the fifo is flushed before we ask the psp to process the commands. Reviewed-by:
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Guchun Chen authored
No need to define the same variables in each loop of the function. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Guchun Chen authored
null ptr should be checked first to avoid null ptr access Signed-off-by:
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Xiaojie Yuan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Hawking Zhang authored
For ASICs like renoir/arct, driver doesn't need to load mec2 jt. when mec1 jt is loaded, mec2 jt will be loaded automatically since the write is actaully broadcasted to both. We need to more time to test other gfx9 asic. but for now we should be able to draw conclusion that mec2 jt is not needed for renoir and arct. Signed-off-by:
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Hawking Zhang authored
enable psp block for firmware loading and other security feature setup. Signed-off-by:
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Kai-Heng Feng authored
Laptops with AMD APU doesn't restore display backlight brightness after system resume. This issue started when DC was introduced. Let's use BL_CORE_SUSPENDRESUME so the backlight core calls update_status callback after system resume to restore the backlight level. Tested on Dell Inspiron 3180 (Stoney Ridge) and Dell Latitude 5495 (Raven Ridge). Signed-off-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
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Alex Deucher authored
We are reserving vram pages so they should be aligned to the GPU page size. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Xiaojie Yuan authored
except soc_bounding_box which is not integrated in discovery table yet Signed-off-by:
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Tao Zhou authored
umc retired page belongs to vram and it should be aligned to gpu page size Signed-off-by:
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Prike Liang authored
VCN Gate/Ungate by processing the SMU power up/down message, otherwise S3 will resume failed as JPEG always power off during start VCN stage. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Tianci.Yin authored
Add Navi12 PCI id support. Reviewed-by:
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Tao Zhou authored
There are two cases of reserve error should be ignored: 1) a ras bad page has been allocated (used by someone); 2) a ras bad page has been reserved (duplicate error injection for one page); DRM_ERROR is unnecessary for the failure of bad page reserve Signed-off-by:
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Adam Zerella authored
Some of the documentation formatting could be improved which will resolve some Sphinx amdgpu build warnings e.g WARNING: Unexpected indentation. WARNING: Block quote ends without a blank line; unexpected unindent. WARNING: Inline emphasis start-string without end-string. Signed-off-by:
Adam Zerella <adam.zerella@gmail.com> Signed-off-by:
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Alex Deucher authored
Add new parameters. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Yong Zhao authored
These were deleted before, but somehow showed up again. Delete them again. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] HDCP is not fully finished, so we need to be able to build and run the driver without it. [How] Add a Kconfig to toggle it Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We don't support HDCP for pre RAVEN asics [How] Check if we are RAVEN+. Use this to attach the content_protection property, this way usermode can't try to enable HDCP on pre DCN asics. Also we need to update the module on hpd so guard it aswell Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to use HW state to set content protection to ENABLED. This way we know that the link is encrypted from the HW side [How] Create a workqueue that queries the HW every ~2seconds, and sets it to ENABLED or DESIRED based on the result from the hardware Signed-off-by:
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Bhawanpreet Lakha authored
[Why] This is needed for DP as DP can send us info using irq. [How] Check if irq bit is set on short pulse and call the function that handles cpirq in amdgpu_dm_hdcp Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to manage the content protection property changes for different usecase, once cp is DESIRED we need to maintain the ENABLED/DESIRED status for different cases. [How] 1. Attach the content_protection property 2. HDCP enable (UNDESIRED -> DESIRED) call into the module with the correct parameters to start hdcp. Set cp to ENABLED 3. HDCP disable (ENABLED -> UNDESIRED) Call the module to disable hdcp. 3. Handle Special cases (Hotplug, S3, headless S3, DPMS) If already ENABLED: set to DESIRED on unplug/suspend/dpms, and disable hdcp Then on plugin/resume/dpms: enable HDCP Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need this to enable HDCP on linux, as we need events to interact with the hdcp module [How] Add work queue to display manager and handle the creation and destruction of the queue Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to read and write specific i2c and dpcd messages. [How] Created static functions for packing the dpcd and i2c messages for hdcp. Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to interact with the hdcp module from the DM, the module has to be interacted with in terms of events [How] Create the files needed for linux hdcp. These files manage the events needed for the dm to interact with the hdcp module. We use the kernel work queue to process the events needed for the module Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to update the hdcp display parameter whenever the link is updated, so the next time there is an update to hdcp we have the latest display info [How] Create a callback, and use this anytime there is a change in the link. This will be used later by the dm. Signed-off-by:
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Bhawanpreet Lakha authored
[Why] All the HDCP transactions should be verified using PSP. [How] This patch calls psp with the correct inputs to verify the steps of authentication. Signed-off-by:
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Bhawanpreet Lakha authored
This module manages HDCP for amdgpu driver. The module behaves as a state machine which handles the different authentication states of HDCP The module is divided into 3 major components +--------+ | Hdcp.c | +--------+ Manages the state machine, sends the events to be executed and communicates with the dm +-----------+ |Execution.c| +-----------+ This executes events based on the current state. Also generates execution results as transition inputs +------------+ |Transition.c| +------------+ Decides the next state based on the input and makes requests to hdcp.c to handle. +-------------+ ------> | Execution.c | ------ | +-------------+ | | V +----+ +--------+ +--------------+ | DM | -----> | Hdcp.c | <------------ | Transition.c | +----+ <----- +--------+ +--------------+ v2: Drop unused function definitions Signed-off-by:Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
DTM is the display topology manager. This is needed to communicate with psp about the display configurations. This patch adds -Loading the firmware -The functions and definitions for communication with the firmware v2: Fix formatting Signed-off-by: -
Bhawanpreet Lakha authored
This patch adds -Loading the firmware -The functions and definitions for communication with the firmware v2: Fix formatting Signed-off-by:
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Aric Cyr authored
[Why] There can be some unsynchronized frames when entering/exiting LFC. This may cause tearing or stuttering at such transitions. [How] Add a enter/exit margin to algorithm to smoothly transition into and out of LFC without desynchronizing frames. Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Reza Amini <Reza.Amini@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
Detile buffer size affects dcc caps and therefore needs to be corrected for each ip. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Martin Leung authored
tg_inst may be used uninitialized, so initialize it to 0. Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
Jaehyun Chung <Jaehyun.Chung@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Zhan Liu authored
[Why] When more than 2 displays are connected to the graphics card, only the minimum memory clock is needed. However, when more displays are connected, the minimum memory clock is not sufficient enough to support the overwhelming bandwidth. System will hang under this circumstance. Also, the old code didn't address HBM cards, which has 2 pseudo channels. We need to add the HBM part here. [How] When graphics card connects to 2 or more displays, switch to high memory clock. Also, choose memory multiplier based on whether its regular DRAM or HBM. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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